SLG46621V-DIP Silego

SLG46621 GreenPAK Programmable Mixed-signal Matrix with Dual Supply Features Pin Configuration Logic & Mixed Signal Circuits Highly Versatile Macrocells Read Back Protection (Read Lock) 1.8 V (5%) to 5 V (10%) VDD VDD 1 17 GPIO 1.8 V (5%) to 5 V (10%) VDD2 (VDD2 VDD) 2 16 Operating Temperature Range: -40C to 85C GPI 20 19 18 GPIO RoHS Compliant / Halogen-Free 3 15 GPIO GPIO 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch 4 14 GPIO VDD2 Applications GPIO 5 13 GPIO Personal Computers and Servers 8 9 10 GPIO 6 12 GPIO PC Peripherals 7 11 GPIO GND Consumer Electronics Data Communications Equipment STQFN-20 Handheld and Portable Electronics (Top View) Block Diagram LF Oscillator RC Oscillator Pin 20 Pin 19 Pin 18 GPIO GPIO GPIO Ring Oscillator PWR DET Pin 1 Pin 17 VDD GPIO Counters/Delay Generators Programmable ACMP0 Delay0 CNT0 CNT1 CNT2 CNT3 CNT4 Pin 2 Pin 16 GPI GPIO CNT5 CNT6 CNT7 CNT8 CNT9 Programmable Delay1 ACMP1 DFF/Latches Pin 3 Pin 15 GPIO GPIO DFF0 DFF1 DFF2 DFF3 DFF4 DFF5 Pipe Vref Delay0 ACMP2 DFF6 DFF7 DFF8 DFF9 DFF10 DFF11 Pin 4 Pin 14 Pipe POR GPIO VDD2 Delay1 Look Up Tables (LUTs) 2-bit 2-bit 2-bit 2-bit 2-bit ACMP3 LUT2 0 LUT2 1 LUT2 2 LUT2 3 LUT2 4 Additional Pin 5 Logic Functions Pin 13 2-bit 2-bit 2-bit 3-bit 3-bit GPIO GPIO LUT2 5 LUT2 6 LUT2 7 LUT3 0 LUT3 1 INV 0 INV 1 3-bit 3-bit 3-bit 3-bit 3-bit ACMP4 LUT3 2 LUT3 3 LUT3 4 LUT3 5 LUT3 6 Pin 6 Pin 12 3-bit 3-bit 3-bit 3-bit 3-bit Combination Function GPIO GPIO LUT3 7 LUT3 8 LUT3 9 LUT3 10 LUT3 11 Macrocell 4-bit LUT4 1 3-bit 3-bit 3-bit 3-bit 4-bit ACMP5 or PGEN LUT3 12 LUT3 13 LUT3 14 LUT3 15 LUT4 0 Pin 7 Pin 11 GPIO GND 8-bit SAR PGA DAC0 DAC1 Pin 8 Pin 9 Pin 10 ADC GPIO GPIO GPIO 2019 Dialog Semiconductor Revised October 28, 2019 Revision 1.36 GPIO GPIO GPIO GPIO GPIO GPIOSLG46621 1.0 Overview The SLG46621 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46621. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The additional power supply (VDD2) on the SLG46621 provides the ability to interface two independent voltage domains within the same design. Users can configure pins, dedicated to each power supply, as inputs, outputs, or both (controlled dynamically by internal logic) to both VDD and VDD2 voltage domains. Using the available macrocells designers can implement mixed-signal functions bridging both domains or simply pass through level-translation in both High to Low and Low to High directions. The macrocells in the device include the following: 8-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) ADC 3-bit Programmable Gain Amplifier (PGA) Two Digital-to-Analog Converters (DAC) Six Analog Comparators (ACMP) Two Voltage References (VREF) Twenty Five Combinatorial Look Up Tables (LUTs) Eight 2-bit LUTs Sixteen 3-bit LUTs One 4-bit LUT One Combination Function Marcocells Pattern Generator or 4-bit LUT Three Digital Comparators/Pulse Width Modulators (DCMPs /PWMs) w/ Selectable Deadband Ten Counters/Delays (CNT/DLY) Two 14-bit Delay/Counter One 14-bit Delay/Counter (Wake-Sleep Control) One 14-bit Delay/Counter/Finite State Machine Five 8-bit Delay/Counter One 8-bit Delay/Counter/Finite State Machine Twelve D Flip-flops/Latches Two Pipe Delays 16 stage/2 output Two Programmable Delays w/ Edge Detection Three Internal Oscillators Low-Frequency Ring RC 25 kHz and 2 MHz Power-On-Reset (POR) Two Bandgaps Slave SPI 2019 Dialog Semiconductor Page 1 of 214 Revision 1.36