SLG46722V-DIP Silego

SLG46722 GreenPAK Programmable Mixed Signal Array Features Pin Configuration Logic & Mixed Signal Circuits Highly Versatile Macrocells Read Back Protection (Read Lock) 1.8V (5%) to 5V (10%) Supply Operating Temperature Range: -40C to 85C VDD 1 17 GPIO RoHS Compliant / Halogen-Free 2 16 GPI 20 19 18 GPIO 20-pin STQFN: 2 x 3 x 0.55 mm, 0.4 mm pitch 3 15 GPIO GPIO Applications 4 14 GPIO GPIO Personal Computers and Servers GPIO 5 13 GPIO PC Peripherals 8 9 10 GPIO 6 12 GPIO Consumer Electronics Data Communications Equipment 7 11 GPIO GND Handheld and Portable Electronics STQFN-20 (Top View) Block Diagram Pin 20 Pin 19 Pin 18 GPIO GPIO GPIO Pin 17 Pin 1 GPIO VDD Counters/Delay Generators D Flip Flops (DFF) / Latches Pin 16 CNT0 CNT1 CNT2 CNT3 DFF0 DFF1 DFF2 Pin 2 GPIO GPI CNT4 CNT5 CNT6 CNT7 DFF3 DFF5 DFF6 Pin 15 Pin 3 GPIO GPIO Combination Function Macrocells Programmable 2-bit LUT2 0 3-bit LUT3 8 Delay or or Pin 14 Pin 4 DFF4 Pipe Delay GPIO GPIO RC Oscillator Look Up Tables (LUTs) Pin 13 Pin 5 GPIO GPIO 2-bit 2-bit 3-bit 2-bit 2-bit LUT2 1 LUT2 2 LUT3 3 LUT2 4 LUT2 5 3-bit 3-bit 3-bit 3-bit 3-bit Additional Logic Functions LUT3 0 LUT3 1 LUT3 2 LUT3 3 LUT3 4 Pin 12 Pin 6 GPIO GPIO 3-bit 3-bit 3-bit 3-bit 4-bit FILTER 0 FILTER 1 LUT3 5 LUT3 6 LUT3 7 LUT3 9 LUT4 0 Pin 11 Pin 7 GND GPIO Pin 8 Pin 9 Pin 10 GPIO GPIO GPIO Revised October 29, 2019 2019 Dialog Semiconductor Revision 1.16 GPIO GPIO GPIO GPIO GPIO GPIOSLG46722 1.0 Overview The SLG46722 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Memory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46722. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following: Fifteen Combinatorial Look Up Tables (LUTs) Five 2-bit LUTs Nine 3-bit LUTs One 4-bit LUT Two Combination Function Macrocell One Selectable FF/Latch or 2-bit LUT One Selectable Pipe Delay or 3-bit LUT Pipe Delay 16 stage / 3 output Eight Counter / Delay Generators (CNT/DLY) Two 14-bit delay/counter One 14-bit delay/counter with external clock/reset Three 8-bit delays/counters Two 8-bit delays/counters with external clock/reset Six D Flip-Flop / Latches (DFF) Pipe Delay 16 stage/3 output (Part of Combination Function Macrocell) Programmable Delay Additional Logic Functions 2 Deglitch Filters RC Oscillator (RC OSC) 2019 Dialog Semiconductor Revision 1.16 Page 1 of 84