SLG7NT4083V Silego

SLG7NT4083 SLG7NT4083 POWER GOOD DETECTOR General Description Pin Configuration Silego SLG7NT4083 is a low power and small form device. The SoC is housed in a 2.5mm x 2.5mm VDD 1 12 SYS PWROK TDFN package which is optimal for using with small DLY PWRGD IN 2 11 ALL SYS PWRGD devices. M RAIL PWRGD 3 10 SYS RAIL PWRGD V1.05S PWRGD 4 9 VCCST PWRGD SLP M N 5 8 SLP S3 N Features Low Power Consumption MPWROK 6 7 GND 3.3V Supply Voltage TDFN-12 Thermal Pad RoHS Compliant / Halogen-Free connected to GND TOP VIEW Pb-Free TDFN-12 Package Output Summary 1 Output Open Drain 3 Outputs Push Pull Block Diagram Silego Technology, Inc. Rev 1.02 SLG7NT4083 DB r102 Revised December 11, 2012 SLG7NT4083 GP r005 SLG7NT4083 POWER GOOD DETECTOR Typical Application Circuit +V3.3A +V1.05S VCCST C1 R1 100nF 10k U1 1 12 SYS PWROK OUT VDD data I/O DLY PWRGD IN 2 11 ALL SYS PWRGD IN OUT data I data I/O M RAIL PWRGD 3 10 IN data I/O data I/O V1.05S PWRGD 4 9 VCCST PWRGD IN OUT data I/O data I/O SLP M N 5 8 IN data I/O data I/O 6 7 data I/O GND SLG7NT4083 SLP S3 N IN MPWROK OUT SYS RAIL PWRGD IN Page 2 SLG7NT4083 DB r102