536FB212M500DGR Silicon Labs

Si535/536 REVISION D ULTRA LOW JITTER CRYSTAL OSCILLATOR (XO) Features Si5602 Available with select frequencies from Available with LVPECL and 100 MHz to 312.5 MHz LVDS outputs rd 3.3 and 2.5 V supply options 3 generation DSPLL with superior Industry-standard 5 x 7 mm jitter performance and high-power package and pinout supply noise rejection Pb-free/RoHS-compliant 3x better frequency stability than SAW-based oscillators Ordering Information: Applications See page 7. 10/40/100G data centers Enterprise servers 10G Ethernet switches/routers Networking Fibre channel/SAS/storage Telecommunications Pin Assignments: See page 6. Description The Si535/536 XO utilizes Silicon Labs advanced DSPLL circuitry to (Top View) provide an ultra low jitter clock at high-speed differential frequencies. Unlike a traditional XO, where a different crystal is required for each output frequency, 1 6 V NC DD the Si535/536 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide OE 2 5 CLK exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in GND 3 4 CLK+ communication systems. The Si535/536 IC based XO is factory programmed at time of shipment, thereby eliminating long lead times associated with Si535 custom oscillators. Functional Block Diagram V 1 6 DD OE V CLK CLK+ DD NC 2 5 CLK GND 3 4 CLK+ Si536 Fixed 100312.5 MHz Frequency DSPLL XO Clock Synthesis OE GND Rev. 1.3 6/18 Copyright 2018 by Silicon Laboratories Si535/536Si535/536 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit 1 V 3.3 V option 2.97 3.3 3.63 V Supply Voltage DD 2.5 V option 2.25 2.5 2.75 V Supply Current I Output enabled DD LVPECL 111 121 mA LVDS 90 98 60 mA Tristate mode 75 2 V Output Enable (OE) V 0.75 x V IH DD V V 0.5 IL Operating Temperature Range T 40 85 C A Notes: 1. Selectable parameter specified by part number. See Section 3.Ordering Informatio on page 7 for further details. 2. OE pin includes a 17 k pullup resistor to V . DD Table 2. CLK Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Unit 1 f LVPECL/LVDS 100 312.5 MHz Nominal Frequency O Initial Accuracy Measured at +25 C at time of f 1.5 ppm i shipping 1,2 Temperature Stability 7 +7 ppm 20 +20 Aging Frequency drift over first year 3 ppm f a Frequency drift over 20 year 10 ppm life 2 Total Stability Temp stability = 20 ppm 31.5 ppm Temp stability = 7 ppm 20 3 Powerup Time t T = 40C +85C 10 ms OSC A Notes: 1. See Section 3.Ordering Informatio on page 7 for the list of available frequencies. 2. Selectable parameter specified by part number. 3. Time from powerup or tristate mode to f . O 2 Rev. 1.3