Si550 REVISION D VOLTAGE-CONTROLLED CRYSTAL OSCILLATOR (VCXO) 10 MHZ TO 1.4 GHZ Features Available with any-rate output Internal fixed crystal frequency Si5602 frequencies from 10 to 945 MHz ensures high reliability and low and selected frequencies to aging 1.4 GHz Available CMOS, LVPECL, LVDS, and CML outputs 3rd generation DSPLL with 3.3, 2.5, and 1.8 V supply options superior jitter performance Industry-standard 5 x 7 mm 3x better frequency stability than package and pinout SAW-based oscillators Lead-free/RoHS-compliant Ordering Information: Applications See page 8. SONET/SDH Low-jitter clock generation xDSL Optical modules Pin Assignments: 10 GbE LAN/WAN Clock and data recovery See page 7. Description (Top View) The Si550 VCXO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low-jitter clock at high frequencies. The Si550 is available with V V C 1 6 DD any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional VCXOs, where a different crystal is required for OE 2 5 CLK each output frequency, the Si550 uses one fixed crystal to provide a wide range of output frequencies. This IC-based approach allows the crystal GND 3 4 CLK+ resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems. The Si550 IC-based VCXO is factory-configurable for a wide variety of user specifications, including frequency, supply voltage, output format, tuning slope, and temperature stability. Specific configurations are factory programmed at time of shipment, thereby eliminating the long lead times associated with custom oscillators. Functional Block Diagram V CLK CLK+ DD Any-rate Fixed 10-1400 MHz Frequency DSPLL XO Clock Synthesis ADC Vc OE GND Rev. 0.6 6/07 Copyright 2007 by Silicon Laboratories Si550Si550 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Units 1 V 3.3 V option 2.97 3.3 3.63 Supply Voltage DD 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 Supply Current I Output enabled DD LVPECL 130 120 CML 108 117 mA 99 LVDS 108 90 CMOS 98 tristate mode 60 75 2 Output Enable (OE) V 0.75 x V IH DD V V 0.5 IL Operating Temperature Range T 40 85 C A Notes: 1. Selectable parameter specified by part number. See 3.Ordering Informatio on page 8 for further details. 2. OE pin includes a 17 k resistor to V . DD Table 2. V Control Voltage Input C Parameter Symbol Test Condition Min Typ Max Units 1,2,3 Control Voltage Tuning Slope K 10 to 90% of V 33 ppm/V V DD 45 90 135 180 356 4 Control Voltage Linearity L BSL 5 1 +5 VC % Incremental 10 5 +10 Modulation Bandwidth BW 9.3 10.0 10.7 kHz V Input Impedance Z 500 k C VC Nominal Control Voltage V f V /2 V CNOM O DD Control Voltage Tuning Range V 0V V C DD Notes: 1. Positive slope selectable option by part number. See 3.Ordering Informatio on page 8. 2. For best jitter and phase noise performance, always choose the smallest K that meets the applications minimum APR V requirements. See AN266: VCXO Tuning Slope (K ), Stability, and Absolute Pull Range (APR) for more information. V 3. K variation is 10% of typical values. V 4. BSL determined from deviation from best straight line fit with V ranging from 10 to 90% of V . Incremental slope C DD determined with V ranging from 10 to 90% of V . C DD 2 Rev. 0.6