Si590/591 1 ps MAX JITTER CRYSTAL OSCILLATOR (XO) (10 MHZ TO 810 MHZ) Features Si5602 Available with any-frequency output Available CMOS, LVPECL, frequencies from 10 to 810 MHz LVDS, and CML outputs 3.3, 2.5, and 1.8 V supply options 3rd generation DSPLL with superior Industry-standard 5 x 7 mm jitter performance: 1 ps max jitter package and pinout Better frequency stability than SAW- Pb-free/RoHS-compliant based oscillators 40 to +85 C operating Internal fundamental mode crystal temperature range ensures high reliability Ordering Information: Applications See page 7. SONET/SDH (OC-3/12/48) Test and measurement Networking Storage Pin Assignments: SD/HD SDI/3G SDI video FPGA/ASIC clock generation See page 6. Description (Top View) The Si590/591 XO utilizes Silicon Laboratories advanced DSPLL circuitry to provide a low jitter clock at high frequencies. The Si590/591 supports any frequency from 10 to 810 MHz. Unlike a traditional XO, where a unique 1 6 V NC DD crystal is required for each output frequency, the Si590/591 uses one fixed crystal to provide a wide range of output frequencies. This IC based OE 2 5 CLK approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior GND 3 4 supply noise rejection, simplifying the task of generating low jitter clocks in CLK+ noisy environments typically found in communication systems. The Si590/591 IC based XO is factory configurable for a wide variety of user Si590 (LVDS/LVPECL/CML) specifications including frequency, supply voltage, output format, and stability. Specific configurations are factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. V 1 6 DD OE Functional Block Diagram NC 2 5 NC V CLK CLK+ DD GND 3 4 CLK Si590 (CMOS) 17 k * Any-rate Fixed 10810 MHz V 1 6 DD OE OE Frequency DSPLL XO Clock Synthesis NC 2 5 CLK 17 k * GND 3 4 CLK+ Si591 (LVDS/LVPECL/CML) *Note: Output Enable High/Low Options Available See Ordering Information GND Rev. 1.0 8/11 Copyright 2011 by Silicon Laboratories Si590/591Si590/591 1. Electrical Specifications Table 1. Recommended Operating Conditions Symbol Test Condition Min Typ Max Units Parameter 1 V 3.3 V option 2.97 3.3 3.63 Supply Voltage DD 2.5 V option 2.25 2.5 2.75 V 1.8 V option 1.71 1.8 1.89 Supply Current I Output enabled DD LVPECL 110 125 CML 100 110 mA LVDS 90 100 CMOS 80 90 Tristate mode 60 75 2 Output Enable (OE) V 0.75 x V IH DD V V 0.5 IL Operating Temperature Range T 40 85 C A Notes: 1. Selectable parameter specified by part number. See Section 3.Ordering Informatio on page 7 for further details. 2. OE pin includes an internal 17 k pullup resistor to V for output enable active high or a 17 k pull-down resistor to DD GND for output enable active low. See 3.Ordering Informatio on page 7. Table 2. CLK Output Frequency Characteristics Symbol Test Condition Min Typ Max Units Parameter 1,2 f LVPECL/LVDS/CML 10 810 Nominal Frequency O MHz CMOS 10 160 Initial Accuracy Measured at +25 C at time of f 1.5 ppm i shipping Total Stability Note 3, second option code D 20 ppm Note 3, second option code C 30 ppm Note 4, second option code B 50 ppm Note 4, second option code A 100 ppm Temperature Stability second option code D 7 ppm second option code C 20 ppm second option code B 25 ppm second option code A 50 ppm 5 Powerup Time t 10 ms OSC Notes: 1. See Section 3.Ordering Informatio on page 7 for further details. 2. Specified at time of order by part number. 3. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 10 years aging at 40 C. See 3.Ordering Informatio on page 7. 4. Includes initial accuracy, temperature, shock, vibration, power supply and load drift, and 15 years aging at 70 C. See 3.Ordering Informatio on page 7. 5. Time from powerup or tristate mode to f . O 2 Rev. 1.0