C8051F018 C8051F019 Mixed-Signal 16KB ISP FLASH MCU Family ANALOG PERIPHERALS HIGH SPEED 8051 C CORE - Pipelined Instruction Architecture Executes 70% of - SAR ADC Instruction Set in 1 or 2 System Clocks 10-bit - Up to 25MIPS Throughput with 25MHz Clock 1LSB INL No Missing Codes - Expanded Interrupt Handler Programmable Throughput up to 100ksps Up to 8 External Inputs Programmable as Single- MEMORY Ended or Differential - 1280 (256 + 1k) Bytes Internal Data RAM Data Dependent Windowed Interrupt Generator - 16k Bytes FLASH In-System Programmable in 512 byte Built-in Temperature Sensor ( 3 C) Sectors - Two Analog Comparators DIGITAL PERIPHERALS Programmable Hysteresis Values - 4 Byte-Wide Port I/O All are 5V tolerant Configurable to Generate Interrupts or Reset TM TM TM - Hardware SMBus (I2C Compatible), SPI , and UART - Voltage Reference Serial Ports Available Concurrently 2.4V 15 ppm/C - Programmable 16-bit Counter/Timer Array with Five Available on External Pin Capture/Compare Modules - Precision VDD Monitor/Brown-out Detector - Four General Purpose 16-bit Counter/Timers - Dedicated Watch-Dog Timer ON-CHIP JTAG DEBUG & BOUNDARY SCAN - Bi-directional Reset - On-Chip Debug Circuitry Facilitates Full Speed, Non- Intrusive In-System Debug (No Emulator Required ) CLOCK SOURCES - Provides Breakpoints, Single Stepping, Watchpoints, Stack - Internal Programmable Oscillator: 2-to-16MHz Monitor - External Oscillator: Crystal, RC,C, or Clock - Inspect/Modify Memory and Registers - Can Switch Between Clock Sources on-the-fly Useful in - Superior Performance to Emulation Systems Using ICE- Power Saving Modes Chips, Target Pods, and Sockets SUPPLY VOLTAGE ........................ 2.8V to 3.6V - IEEE1149.1 Compliant Boundary Scan - Typical Operating Current: 12.5mA 25MHz - Low Cost Development Kit - Multiple Power Saving Sleep and Shutdown Modes 64-Pin TQFP, 48-Pin TQFP Temperature Range: 40 C to +85 C ANALOG PERIPHERALS DIGITAL I/O TEMP PCA SENSOR 10-Bit SMBus SAR SPI Bus ADC UART VREF Timer 0 + Timer 1 + - Timer 2 - VOLTAGE Timer 3 COMPARATORS HIGH-SPEED CONTROLLER CORE 8051 CPU CLOCK DEBUG JTAG (25MIPS) CIRCUIT CIRCUITRY 16KB 1280 B 21 SANITY ISP FLASH SRAM INTERRUPTS CONTROL Rev. 1.2 11/03 Copyright 2003 by Silicon Laboratories Not Recommended for New Designs AMUX CROSSBAR Port 3 Port 2 Port 1 Port 0C8051F018 C8051F019 TABLE OF CONTENTS 1. SYSTEM OVERVIEW ......................................................................................................... 7 Table 1.1. Product Selection Guide ..................................................................................................................... 7 Figure 1.1. C8051F018 Block Diagram .............................................................................................................. 8 Figure 1.2. C8051F019 Block Diagram .............................................................................................................. 9 TM 1.1. CIP-51 CPU ............................................................................................................................................. 10 Figure 1.3. Comparison of Peak MCU Execution Speeds ................................................................................. 10 Figure 1.4. On-Board Clock and Reset .............................................................................................................. 11 1.2. On-Board Memory ...................................................................................................................................... 12 Figure 1.5. On-Board Memory Map .................................................................................................................. 12 1.3. JTAG Debug and Boundary Scan ............................................................................................................... 13 Figure 1.6. Debug Environment Diagram ......................................................................................................... 13 1.4. Programmable Digital I/O and Crossbar ..................................................................................................... 14 Figure 1.7. Digital Crossbar Diagram ................................................................................................................ 14 1.5. Programmable Counter Array ...................................................................................................................... 15 Figure 1.8. PCA Block Diagram ....................................................................................................................... 15 1.6. Serial Ports ................................................................................................................................................... 15 1.7. Analog to Digital Converter ........................................................................................................................ 16 Figure 1.9. ADC Diagram ................................................................................................................................. 16 1.8. Comparators ................................................................................................................................................. 17 Figure 1.10. Comparator Diagram ..................................................................................................................... 17 2. ABSOLUTE MAXIMUM RATINGS* .............................................................................. 18 3. GLOBAL DC ELECTRICAL CHARACTERISTICS .................................................... 18 4. PINOUT AND PACKAGE DEFINITIONS ..................................................................... 19 Table 4.1. Pin Definitions .................................................................................................................................. 19 Figure 4.1. TQFP-64 Pinout Diagram ............................................................................................................... 21 Figure 4.2. TQFP-64 Package Drawing ............................................................................................................ 22 Figure 4.3. TQFP-48 Pinout Diagram ............................................................................................................... 23 Figure 4.4. TQFP-48 Package Drawing ............................................................................................................ 24 5. ADC ...................................................................................................................................... 25 Figure 5.1. 10-Bit ADC Functional Block Diagram .......................................................................................... 25 5.1. Analog Multiplexer ...................................................................................................................................... 25 5.2. ADC Modes of Operation ............................................................................................................................ 26 Figure 5.2. 10-Bit ADC Track and Conversion Example Timing ..................................................................... 27 Figure 5.3. Temperature Sensor Transfer Function ........................................................................................... 27 Figure 5.4. AMX0CF: AMUX Configuration Register ..................................................................................... 28 Figure 5.5. AMX0SL: AMUX Channel Select Register (C8051F01x) ............................................................. 29 Figure 5.6. ADC0CF: ADC Configuration Register (C8051F01x) ................................................................... 30 Figure 5.7. ADC0CN: ADC Control Register ................................................................................................... 31 Figure 5.8. ADC0H: ADC Data Word MSB Register ...................................................................................... 32 Figure 5.9. ADC0L: ADC Data Word LSB Register ....................................................................................... 32 5.3. ADC Programmable Window Detector ....................................................................................................... 33 Figure 5.10. ADC0GTH: ADC Greater-Than Data High Byte Register ........................................................... 33 Figure 5.11. ADC0GTL: ADC Greater-Than Data Low Byte Register ............................................................ 33 Figure 5.12. ADC0LTH: ADC Less-Than Data High Byte Register ................................................................ 33 Figure 5.13. ADC0LTL: ADC Less-Than Data Low Byte Register ................................................................. 33 Figure 5.14. 10-Bit ADC Window Interrupt Examples, Right Justified Data ................................................... 34 Figure 5.15. 10-Bit ADC Window Interrupt Examples, Left Justified Data ..................................................... 35 Table 5.1. 10-Bit ADC Electrical Characteristics .............................................................................................. 36 6. COMPARATORS ............................................................................................................... 37 Figure 6.1. Comparator Functional Block Diagram .......................................................................................... 37 Figure 6.2. Comparator Hysteresis Plot ............................................................................................................. 38 Rev. 1.2 2 Not Recommended for New Designs