C8051F2xx 8K ISP FLASH MCU Family Analog Peripherals Memory - SAR ADC - 256 bytes internal data RAM 12-bit resolution ( F206) - 1024 bytes XRAM (available on F206/226/236) 8-bit resolution ( F220/1/6) - 8 kB Flash In-system programmable in 512 byte 1/4 LSB INL (8-bit) and 2 LSB INL (12-bit) Up to 100 ksps sectors Up to 32 channel input multiplexer each port Digital Peripherals I/O pin can be an ADC input - Four byte wide Port I/O All are 5 V tolerant - Two Comparators - Hardware UART and SPI bus 16 programmable hysteresis states Configurable to generate interrupts or reset - 3 general purpose 16-bit counter/timers - V monitor and brown-out detector DD - Dedicated watch-dog timer On-Chip JTAG Debug - Bi-directional reset - On-chip debug circuitry facilitates full speed, - System clock: internal programmable oscillator, non-intrusive in-system debug (No emulator external crystal, external RC, or external clock required) Supply Voltage 2.7 to 3.6 V - Provides breakpoints, single-stepping, watchpoints, - Typical operating current: 10 mA 25 MHz stack monitor - Multiple power saving sleep and shutdown modes - Inspect/modify memory and registers (48-Pin TQFP and 32-Pin LQFP Version - Superior performance to emulation systems using Available) ICE-chips, target pods, and sockets Temperature Range: 40 to +85 C - Complete, low cost development kit High Speed - 8051 mC Core - Pipelined Instruction Architecture Executes 70% of Instructions in 1 or 2 System Clocks - Up to 25MIPS Throughput with 25MHz Clock - Expanded Interrupt Handler ANALOG PERIPHERALS DIGITAL I/O SPI Bus SAR PGA UART ADC Timer 0 + + Timer 1 - - VOLTAGE Timer 2 COMPARATORS HIGH-SPEED CONTROLLER CORE 8051 CPU CLOCK EMULATION JTAG (25MIPS) CIRCUIT CIRCUITRY 8K x 8 1280 x 8 SANITY 22 INTERRUPTS ISP FLASH SRAM CONTROL Rev. 1.6 3/05 Copyright 2005 by Silicon Laboratories C8051F2xx AMUX Digital MUX Port 3 Port 2 Port 1 Port 0C8051F2xx NOTES: 2 Rev. 1.6