C8051F300DK Silicon Labs

C8051F300/1/2/3/4/5 Mixed Signal ISP Flash MCU Family Analog Peripherals High Speed 8051 c Core - 8-Bit ADC ( F300/2 only) - Pipelined instruction architecture executes 70% of Up to 500 ksps instructions in 1 or 2 system clocks Up to 8 external inputs - Up to 25 MIPS throughput with 25 MHz clock Programmable amplifier gains of 4, 2, 1, & 0.5 VREF from external pin or V - Expanded interrupt handler DD Built-in temperature sensor Memory External conversion start input - 256 bytes internal data RAM - Comparator Programmable hysteresis and response time - Up to 8 kB (F300/1/2/3), 4 kB (F304), or 2 kB Configurable as interrupt or reset source (F305) Flash 512 bytes are reserved in the 8 kB Low current (<0.5 A) devices On-chip Debug Digital Peripherals - On-chip debug circuitry facilitates full speed, - 8 Port I/O All 5 V tolerant with high sink current non-intrusive in-system debug (no emulator - Hardware enhanced UART and SMBus serial required) ports - Provides breakpoints, single stepping, - Three general-purpose 16-bit counter/timers inspect/modify memory and registers - 16-bit programmable counter array (PCA) with three - Superior performance to emulation systems using ICE-chips, target pods, and sockets capture/compare modules - Real time clock mode using PCA or timer and - Complete development kit external clock source Supply Voltage 2.7 to 3.6 V Clock Sources - Typical operating current: 6.6 mA 25 MHz - Internal oscillator: 24.5 MHz with 2% accuracy 14 A 32 kHz supports UART operation - Typical stop mode current: 0.1 A - External oscillator: Crystal, RC, C, or clock (1 or 2 - Temperature range: 40 to +85 C pin modes) - Can switch between clock sources on-the-fly Useful in power saving modes 11-Pin QFN or 14-Pin SOIC Package - QFN Size = 3x3 mm ANALOG DIGITAL I/O PERIPHERALS UART A 8-bit SMBus M PGA 500 ksps PCA U ADC X Timer 0 C8051F300/2 only TEMP Timer 1 + SENSOR Timer 2 - VOLTAGE COMPARATOR PROGRAMMABLE PRECISION INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 8/4/2 kBytes 8051 CPU 256 B SRAM ISP Flash (25MIPS) 12 DEBUG POR WDT INTERRUPTS CIRCUITRY Rev. 2.9 7/08 Copyright 2008 by Silicon Laboratories C8051F300/1/2/3/4/5 CROSSBAR I/O PortC8051F300/1/2/3/4/5 NOTES: 2 Rev. 2.9