C8051F350-TB-K Silicon Labs

C8051F350/1/2/3 8 k ISP Flash MCU Family Analog Peripherals High Speed 8051 C Core - 24 or 16-Bit ADC - Pipelined Instruction architecture; executes 70% of No missing codes instructions in 1 or 2 system clocks 0.0015% nonlinearity - Up to 50 MIPS throughput Programmable conversion rates up to 1 ksps 8-Input multiplexer - Expanded interrupt handler 1x to 128x PGA Memory Built-in temperature sensor - 768 Bytes (256 + 512) On-Chip RAM - Two 8-Bit Current Output DACs - Comparator - 8 kB Flash; In-system programmable in 512-byte Programmable hysteresis and response time Sectors Configurable as interrupt or reset source Digital Peripherals Low current (0.4 A) On-chip Debug - 17 Port I/O; All 5 V tolerant with high sink current - On-chip debug circuitry facilitates full speed, non- - Enhanced UART, SMBus, and SPI Serial Ports intrusive in-system debug (No emulator required) - Four general purpose 16-bit counter/timers - Provides breakpoints, single stepping, - 16-bit programmable counter array (PCA) with three inspect/modify memory and registers capture/compare modules - Superior performance to emulation systems using - Real time clock mode using PCA or timer and exter- ICE-Chips, target pods, and sockets nal clock source - Low Cost, Complete Development Kit Clock Sources Supply Voltage 2.7 to 3.6 V - Internal Oscillator: 24.5 MHz with 2% accuracy - Typical operating current: 5.8 mA @ 25 MHz; supports UART operation 11 A @ 32 kHz - External Oscillator: Crystal, RC, C, or clock - Typical stop mode current: 0.1 A (1 or 2 pin modes) Temperature Range: 40 to +85 C - Clock multiplier to achieve 50 MHz internal clock - Can switch between clock sources on-the-fly 28-Pin QFN or 32-Pin LQFP Package - 5 x 5 mm PCB footprint with 28-QFN ANALOG DIGITAL I/O UART PERIPHERALS Port 0 SMBus 8-bit A IDAC SPI 24/16-bit M 8-bit PCA Port 1 U ADC IDAC Timer 0 X + P2.0 Timer 1 - Timer 2 TEMP VOLTAGE SENSOR Timer 3 COMPARATOR 24.5 MHz PRECISION INTERNAL OSCILLATOR WITH CLOCK MULTIPLIER HIGH-SPEED CONTROLLER CORE 8 kB 8051 CPU 768 B SRAM ISP FLASH (50 MIPS) FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Rev. 1.1 5/07 Copyright 2007 by Silicon Laboratories C8051F35x CROSSBARC8051F350/1/2/3 NOTES: 2 Rev. 1.1