C8051F544-IM Silicon Labs

C8051F54x Mixed Signal ISP Flash MCU Family Analog Peripherals Memory - 12-Bit ADC - 1280 bytes internal data RAM (256 + 1024 XRAM) Up to 200 ksps - 16 or 8 kB Flash In-system programmable in Up to 25 external single-ended inputs 512-byte Sectors VREF from on-chip VREF, external pin or V DD Digital Peripherals Internal or external start of conversion source Built-in temperature sensor - 25 or 18 Port I/O All 5 V tolerant - Two Comparators - LIN 2.1 Controller (Master and Slave capable) no Programmable hysteresis and response time crystal required Configurable as interrupt or reset source Low current - Hardware enhanced UART, SMBus, and On-Chip Debug enhanced SPI serial ports - On-chip debug circuitry facilitates full speed, non- - Four general purpose 16-bit counter/timers intrusive in-system debug (no emulator required) - 16-Bit programmable counter array (PCA) with six - Provides breakpoints, single stepping, capture/compare modules and enhanced PWM inspect/modify memory and registers functionality - Superior performance to emulation systems using Clock Sources ICE-chips, target pods, and sockets - Internal 24 MHz with 0.5% accuracy master LIN - Low cost, complete development kit operation Supply Voltage 1.8 to 5.25 V - External oscillator: Crystal, RC, C, or clock - Typical operating current: 19 mA at 50 MHz (1 or 2 pin modes) Typical stop mode current: 1 A - Can switch between clock sources on-the-fly High-Speed 8051 C Core useful in power saving modes - Pipelined instruction architecture executes 70% of Packages instructions in 1 or 2 system clocks - 32-Pin QFP/QFN (C8051F540/1/4/5) - Up to 50 MIPS throughput with 50 MHz clock - 24-Pin QFN (C8051F542/3/6/7) - Expanded interrupt handler Automotive Qualified - Temperature Range: 40 to +125 C - Compliant to AEC-Q100 ANALOG DIGITAL I/O PERIPHERALS UART 0 Ports 0-3 A 12-bit TEMP M Crossbar SMBus 200 ksps SENSOR U SPI ADC X PCA Timers 0-3 LIN VREG Voltage Comparators 0-1 VREF 24 MHz PRECISION 2x Clock Multiplier INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 16 kB 8051 CPU 1 kB XRAM ISP FLASH (50 MIPS) FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Rev. 1.1 4/11 Copyright 2011 by Silicon Laboratories C8051F540/1/2/3/4/5/6/7C8051F54x 2 Rev. 1.1