C8051F410/1/2/3 2.0 V, 32/16 kB Flash, smaRTClock, 12-bit ADC Analog Peripherals Memory - 12-Bit ADC - 2304 bytes internal data RAM (256 + 2048) 1 LSB INL no missing codes - 32/16 kB Flash In-system programmable in Programmable throughput up to 200 ksps 512 byte sectors Up to 24 external inputs Data dependent windowed interrupt generator - 64 bytes battery-backed RAM (smaRTClock) Built-in temperature sensor (3 C) Digital Peripherals - Two 12-Bit Current Mode DACs - 24 port I/O push-pull or open-drain, up to 5.25 V - Two Comparators tolerance Programmable hysteresis and response time Configurable as wake-up or reset source - Hardware SMBus (I2C Compatible), SPI, and - POR/Brownout Detector UART serial ports available concurrently - V oltage Reference1.5, 2.2 V (programmable) - Four general purpose 16-bit counter/timers On-Chip Debug - Programmable 16-bit counter/timer array with six - On-chip debug circuitry facilitates full-speed, non- capture/compare modules, WDT intrusive in-system debug (No emulator required) - Hardware smaRTClock operates down to 1 V with - Provides breakpoints, single stepping 64 bytes battery-backed RAM and backup voltage - Inspect/modify memory and registers regulator - Complete development kit Clock Sources Supply V oltage 2.0 to 5.25 V - Internal oscillators: 24.5 MHz 2% accuracy supports - Built-in LDO regulator: 2.1 or 2.5 V UART operation clock multiplier up to 50 MHz High Speed 8051 C Core - External oscillator: Crystal, RC, C, or Clock - Pipelined instruction architecture executes 70% of (1 or 2 pin modes) instructions in 1 or 2 system clocks - smaRTClock oscillator: 32 kHz Crystal or - Up to 50 MIPS throughput with self-resonant oscillator 50 MHz system clock - Can switch between clock sources on-the-fly - Expanded interrupt handler 32-Pin LQFP or 28-Pin 5 x 5 QFN T emperature Range: 40 to +85 C Rev. 1.1 11/08 Copyright 2008 by Silicon Laboratories C8051F41xC8051F410/1/2/3 NOTES: 2 Rev. 1.1