C8051F58x/F59x Mixed Signal ISP Flash MCU Family Analog Peripherals Memory - 12-Bit ADC - 8448 bytes internal data RAM (256 + 8192 XRAM) Up to 200 ksps - 128 or 96 kB Banked Flash In-system programma- Up to 32 external single-ended inputs ble in 512-byte Sectors VREF from on-chip VREF, external pin or V DD - External 64 kB data memory interface programma- Internal or external start of conversion source Built-in temperature sensor ble for multiplexed or non-multiplexed mode - Three Comparators Digital Peripherals Programmable hysteresis and response time - 40, 33, or 25 Port I/O All 5 V push-pull with high Configurable as interrupt or reset source sink current Low current On-Chip Debug - CAN 2.0 Controllerno crystal required - On-chip debug circuitry facilitates full speed, non- - LIN 2.1 Controller (Master and Slave capable) no intrusive in-system debug (no emulator required) crystal required - Provides breakpoints, single stepping, - Two Hardware enhanced UARTs, SMBus, and inspect/modify memory and registers enhanced SPI serial ports - Superior performance to emulation systems using - Six general purpose 16-bit counter/timers ICE-chips, target pods, and sockets - Two 16-Bit programmable counter array (PCA) - Low cost, complete development kit peripherals with six capture/compare modules each Supply Voltage 1.8 to 5.25 V and enhanced PWM functionality - Typical operating current: 15 mA at 50 MHz Clock Sources Typical stop mode current: 230 A - Internal 24 MHz with 0.5% accuracy for CAN and High-Speed 8051 C Core master LIN operation. - Pipelined instruction architecture executes 70% of - External oscillator: Crystal, RC, C, or clock instructions in 1 or 2 system clocks (1 or 2 pin modes) - Up to 50 MIPS throughput with 50 MHz clock - Can switch between clock sources on-the-fly useful in power saving modes - Expanded interrupt handler Packages Automotive Qualified - 48-Pin QFP/QFN (C8051F580/1/4/5) - Temperature Range: 40 to +125 C - 40-Pin QFN (C8051F588/9-F590/1) - 32-Pin QFP/QFN (C8051F582/3/6/7) ANALOG DIGITAL I/O PERIPHERALS UART 0-1 Ports 0-4 A 12-bit TEMP M Crossbar SMBus 200 ksps SENSOR U SPI External ADC X Memory PCA x 2 Interface Timers 0-5 CAN VREG Voltage LIN Comparators 0-2 VREF 24 MHz PRECISION 2x Clock Multiplier INTERNAL OSCILLATOR HIGH-SPEED CONTROLLER CORE 128 kB 8051 CPU 8 kB XRAM ISP FLASH (50 MIPS) FLEXIBLE DEBUG POR WDT INTERRUPTS CIRCUITRY Rev 1.5 5/18 Copyright 2018 by Silicon Laboratories C8051F580/1/2/3/4/5/6/7/8/9-F590/1C8051F58x/F59x Table of Contents 1. System Overview ..................................................................................................... 18 2. Ordering Information............................................................................................... 22 3. Pin Definitions.......................................................................................................... 24 4. Package Specifications........................................................................................... 32 4.1. QFP-48 Package Specifications........................................................................ 32 4.2. QFN-48 Package Specifications........................................................................ 34 4.3. QFN-40 Package Specifications........................................................................ 36 4.4. QFP-32 Package Specifications........................................................................ 38 4.5. QFN-32 Package Specifications........................................................................ 40 5. Electrical Characteristics........................................................................................ 42 5.1. Absolute Maximum Specifications..................................................................... 42 5.2. Electrical Characteristics ................................................................................... 43 6. 12-Bit ADC (ADC0)................................................................................................... 54 6.1. Modes of Operation........................................................................................... 55 6.1.1. Starting a Conversion................................................................................ 55 6.1.2. Tracking Modes......................................................................................... 55 6.1.3. Timing ....................................................................................................... 56 6.1.4. Burst Mode................................................................................................ 57 6.2. Output Code Formatting.................................................................................... 59 6.2.1. Settling Time Requirements...................................................................... 59 6.3. Selectable Gain ................................................................................................. 60 6.3.1. Calculating the Gain Value........................................................................ 60 6.3.2. Setting the Gain Value .............................................................................. 62 6.4. Programmable Window Detector....................................................................... 68 6.4.1. Window Detector In Single-Ended Mode .................................................. 70 6.5. ADC0 Analog Multiplexer .................................................................................. 72 7. Temperature Sensor................................................................................................ 74 8. Voltage Reference.................................................................................................... 75 9. Comparators............................................................................................................. 77 9.1. Comparator Multiplexer ..................................................................................... 85 10. Voltage Regulator (REG0)..................................................................................... 89 11. CIP-51 Microcontroller........................................................................................... 91 11.1. Performance.................................................................................................... 91 11.2. Instruction Set.................................................................................................. 93 11.2.1. Instruction and CPU Timing .................................................................... 93 11.3. CIP-51 Register Descriptions .......................................................................... 97 11.4. Serial Number Special Function Registers (SFRs) ....................................... 101 12. Memory Organization .......................................................................................... 102 12.1. Program Memory........................................................................................... 102 12.1.1. MOVX Instruction and Program Memory .............................................. 104 12.2. Data Memory................................................................................................. 104 12.2.1. Internal RAM ......................................................................................... 105 12.2.1.1. General Purpose Registers .......................................................... 105 Rev 1.5 3