C8051F96x Ultra Low Power 128K, LCD MCU Family Ultra Low Power Consumption at 3.6 V High-Speed 8051 C Core - 130 A/MHz Low-Power Active mode with dc-dc - Pipelined instruction architecture executes 70% of enabled instructions in 1 or 2 system clocks Memory - 120 nA sleep current w/ data retention POR monitor - Up to 128 kB Flash In-system programmable Full enabled read/write/erase functionality over supply range - 450 nA sleep mode with SmaRTClock - Up to 8 kB internal data RAM (internal LFO) Digital Peripherals - 600 nA sleep mode with SmaRTClock (ext. crystal) - 57 or 34 port I/O All 5 V tolerant with high sink - 2 s wakeup time 1.5 A analog settling time current and programmable drive strength 12-Bit 16 Ch. Analog-to-Digital Converter 2 - Hardware SMBus (I C Compatible), 2 x SPI, - Up to 75 ksps (12-bit mode) or 300 ksps and UART serial ports available concurrently (10-bit mode) - Four general purpose 16-bit counter/timers - External pin or internal VREF (no ext cap required) - Programmable 16-bit counter/timer array with six - On-chip voltage reference 0.5x gain allows measur- capture/compare modules and watchdog timer ing voltages up to twice the reference voltage Clock Sources - Autonomous burst mode with 16-bit auto-averaging - Precision Internal oscillator: 24.5 MHz, 2% accuracy accumulator supports UART operation spread-spectrum mode - Integrated temperature sensor for reduced EMI Two Low Current Comparators - Low power internal oscillator: 20 MHz - Programmable hysteresis and response time - External oscillator: Crystal, RC, C, or CMOS Clock - Configurable as wake-up or reset source - SmaRTClock oscillator: 32 kHz Crystal or 16.4 kHz Internal 6-Bit Current Reference internal LFO - Up to 500 A source and sink capability On-Chip Debug - Enhanced resolution via PWM interpolation - On-chip debug circuitry facilitates full-speed, non- Integrated LCD Controller intrusive in-system debug (no emulator required) - Supports up to 128 segments (32x4) - Provides 4 breakpoints, single stepping - LCD controller consumes only 400 nA for Packages 32-segment static display - 76-pin DQFN (6 x 6 mm) - Integrated charge pump for contrast control - 40-pin QFN (6 x 6 mm) Metering-Specific Peripherals - 80-pin TQFP (12 x 12 mm) - DC-DC buck converter allows dynamic voltage Temperature Range: 40 to +85 C scaling for maximum efficiency (250 mW output) - Sleep-mode pulse accumulator with programmable switch, de-bounce and pull-up control interfaces directly to metering sensor - Data Packet Processing Engine (DPPE) includes hardware AES, DMA, CRC and encoding blocks for acceleration of wireless protocols Port I/O Configuration CIP-51 8051 Power On P0.0/VREF Controller Core Reset/PMU P0.1/AGND Digital Peripherals Wake 128k Byte ISP Flash P0.2/XTAL1 UART Program Memory Port 0 P0.3/XTAL2 Reset Timers Drivers P0.4/TX 256 Byte SRAM 0, 1, 2, 3 C2CK/RST Debug / P0.5/RX Programming P0.6/CNVSTR Priority 8092 Byte XRAM PCA/WDT Hardware P0.7 Crossbar Decoder P1.0/PC0 SMBus C2D P1.1/PC1 DMA SPI 0 P1.2/XTAL3 VBAT Analog VBAT CRC Port 1 P1.3/XTAL4 Power SPI 1 Engine Drivers P1.4 VDD (DMA Enabled) Digital VREG P1.5/INT5 AES VDC Power Crossbar Control P1.6/INT6 Engine P1.7 Encoder LCD (up to 4x32) SFR P2.0/SCK1 VBATDC DC/DC Buck SYSCLK Bus P2.1/MISO1 Converter EMIF IND P2.2/MOSI1 Precision Port 2 P2.3/NSS1 GNDDC 24.5 MHz Pulse Counter P2.4 Drivers Oscillator P2.5 Low Power Analog Peripherals P2.6 LCD Charge CAP 20 MHz P2.7 Pump Oscillator 32 Internal External P3-6 P3.0...P6.7 XTAL1 External Drivers VREF VREF VDD Oscillator VREF 16 XTAL2 P7 Circuit A 12-bit Temp P7.0/C2D M Driver 75ksps Sensor U Enhanced XTAL3 ADC GND X smaRTClock GND XTAL4 Oscillator CP0, CP0A + - System Clock CP1, CP1A + - Configuration Comparators Rev. 1.0 7/13 Copyright 2013 by Silicon Laboratories C8051F96xC8051F96x 2 Rev. 1.0