C8051F97x Low Power Capacitive Sensing MCU with up to 32 kB of Flash Low Power Consumption High-Speed CIP-51 C Core - 200 A/MHz in active mode (24.5 MHz clock) - Efficient, pipelined instruction architecture - 2 s wakeup time - Up to 25 MIPS throughput with 25 MHz clock - 55 nA sleep mode with brownout detector - Uses standard 8051 instruction set - 280 nA sleep mode with LFO - Expanded interrupt handler - 600 nA sleep mode with external crystal - 1-cycle 16 x 16 MAC Engine - 7-channel Direct Memory Access (DMA) module Capacitance Sense Interface Memory - Supports buttons, sliders, wheels, and proximity sensing - Fast 40 s per channel conversion time - Up to 32 kB flash - 16-bit resolution, up to 43 input channels - Flash is in-system programmable in 512-Byte sectors - Auto scan and wake-on-touch - Up to 8 kB RAM - Auto-accumulate up to 64x samples General-Purpose I/O 10-Bit Analog-to-Digital Converter - Up to 43 pins with high sink current and programmable drive - Up to 43 external pin input channels, up to 300 ksps - Crossbar-enabled - Internal VREF or external VREF supported Timer/Counters and PWM Clock Sources - 4 general purpose 16-bit timer/counters - Internal oscillators: 24.5 MHz, 2% accuracy supports UART - 16-bit Programmable Counter Array (PCA) with three channels operation 20 MHz low power oscillator requires very little bias of PWM, capture/compare, or frequency output capability, and current. watchdog timer - External oscillator: Crystal, RC, C, or CMOS Clock Supply Voltage: 1.8 to 3.6 V - SmaRTClock oscillator: 32 kHz Crystal or internal LFO - Built-in LDO regulator allows a high analog supply voltage and - Can switch between clock sources on-the-fly useful in imple- low digital core voltage menting various power-saving modes - 2 supply monitors (brownout detector) for sleep and active On-Chip Debug modes - On-chip debug circuitry facilitates full speed, non-intrusive in- Package Options system debug (no emulator required) - 24-pin QFN (4x4 mm) - Provides breakpoints, single stepping, inspect/modify memory - 32-pin QFN (5x5 mm) and registers - 48-pin QFN (6x6 mm) Unique Identifier Temperature Ranges: 40 to +85 C - 128-bit unique key for each device Core / Memory / Support Digital Peripherals UART 16-32 kB Flash Core LDO CIP-51 I2C / SMBus HS I2C Slave (25 MHz) 4-8 kB RAM Supply Monitor SPI 16-bit CRC 7 ch. DMA 16 x 16 MAC 4 x 16-bit Timers C2 Serial Debug / Programming 3-Channel PCA / Watchdog Clocking / Oscillators Analog Peripherals 24.5 MHz Precision Oscillator SAR ADC (10-bit 300 ksps) 20 MHz Low Power Oscillator Capacitive Sensing smaRTClock with 16.4 kHz LFO Voltage Reference External Oscillator Temperature Sensor Rev 1.1 12/16 Copyright 2016 by Silicon Laboratories C8051F97x Not Recommended for New Designs Clock Selection Priority Crossbar Flexible Pin Muxing Encoder 43 Multi-Function I/O Pins1. Electrical Characteristics..................................................................................................10 1.1. Electrical Characteristics..............................................................................................10 1.2. Thermal Conditions ......................................................................................................21 1.3. Absolute Maximum Ratings..........................................................................................21 2. System Overview ...............................................................................................................22 2.1. Power ...........................................................................................................................24 2.1.1. Voltage Supply Monitor (VMON0) .......................................................................24 2.1.2. Device Power Modes...........................................................................................24 2.1.3. Suspend Mode.....................................................................................................25 2.1.4. Sleep Mode..........................................................................................................25 2.1.5. Low Power Active Mode ......................................................................................26 2.1.6. Low Power Idle Mode ..........................................................................................26 2.2. I/O.................................................................................................................................26 2.2.1. General Features.................................................................................................26 2.2.2. Crossbar ..............................................................................................................26 2.3. Clocking........................................................................................................................27 2.4. Counters/Timers and PWM..........................................................................................27 2.4.1. Programmable Counter Array (PCA0).................................................................27 2.4.2. Timers (Timer 0, Timer 1, Timer 2, and Timer 3).................................................27 2.5. Communications and other Digital Peripherals ............................................................28 2.5.1. Universal Asynchronous Receiver/Transmitter (UART0) ....................................28 2.5.2. Serial Peripheral Interface (SPI0)........................................................................28 2.5.3. System Management Bus / I2C (SMBus0)..........................................................28 2.5.4. High-Speed I2C Slave (I2CSLAVE0)...................................................................29 2.5.5. 16/32-bit CRC (CRC0).........................................................................................29 2.6. Analog Peripherals.......................................................................................................29 2.6.1. 10-Bit Analog-to-Digital Converter (ADC0)..........................................................29 2.7. Digital Peripherals ........................................................................................................30 2.7.1. Direct Memory Access (DMA0) ...........................................................................30 2.7.2. Multiply and Accumulate (MAC0) ........................................................................30 2.8. Reset Sources..............................................................................................................30 2.9. Unique Identifier ...........................................................................................................30 2.10.On-Chip Debugging .....................................................................................................30 3. Pin Definitions....................................................................................................................31 3.1. C8051F970/3 QFN-48 Pin Definitions..........................................................................31 3.2. C8051F971/4 QFN-32 Pin Definitions..........................................................................35 3.3. C8051F972/5 QFN-24 Pin Definitions..........................................................................38 4. Ordering Information.........................................................................................................41 5. QFN-48 Package Specifications ......................................................................................43 5.1. QFN-48 Package Marking............................................................................................45 6. QFN-32 Package Specifications .......................................................................................46 6.1. QFN-32 Package Marking............................................................................................49 7. QFN-24 Package Specifications .......................................................................................50 7.1. QFN-24 Package Marking............................................................................................53 8. Memory Organization ........................................................................................................54 8.1. Program Memory..........................................................................................................55 Rev 1.1 2 Not Recommended for New Designs