CY2SSTV855 CY2SSTV855 Differential Clock Buffer/Driver Features Functional Description Phase-locked loop (PLL) clock distribution for Double The CY2SSTV855 is a high-performance, very-low-skew, Data Rate Synchronous DRAM applications very-low-jitter zero-delay buffer that distributes a differential clock input pair (SSTL 2) to four differential (SSTL 2) pairs of 1:5 differential outputs clock outputs and one differential pair of feedback clock External feedback pins (FBINT, FBINC) are used to outputs. In support of low power requirements, when synchronize the outputs to the clock input power-down is HIGH, the outputs switch in phase and frequency with the input clock. When power-down is LOW, all SSCG: Spread Aware for electromagnetic outputs are disabled to a high-impedance state and the PLL is interference (EMI) reduction shut down. 28-pin TSSOP package The device supports a low-frequency power-down mode. Conforms to JEDEC DDR specifications When the input is < 20 MHz, the PLL is disabled and the outputs are put in the Hi-Z state. When the input frequency is > 20 MHz, the PLL and outputs are enabled. When AVDD is tied to ground, the PLL is turned off and bypassed with the input reference clock gated to the outputs. The Cypress CY2SSTV855 is Spread Aware and supports tracking of Spread Spectrum clock inputs to reduce EMI Pin Configuration Block Diagram GND 1 28 GND YT0 YC0 YC3 YC0 2 27 PWRDWN Powerdown YT3 YT0 3 26 and test VDDQ VDDQ AVDD 4 25 logic YT1 GND PWRDWN YC1 5 24 CLKINT FBINT 6 23 FBINC CLKINC 7 22 YT2 VDDQ VDDQ YC2 8 21 AVDD FBOUTC 9 20 CLKINT CLKINC AGND FBOUTT 10 19 PLL YT3 FBINT VDDQ VDDQ 11 18 FBINC YC3 YT1 YT2 12 17 YC2 YC1 13 16 FBOUTT GND GND 14 15 FBOUTC 28-pin TSSOP ......................... Document : 38-07459 Rev. *F Page 1 of 6 400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com CY2SSTV855 1, 2 Pin Definition Pin Name I/O Description 6CLKINTI True Clock Input. Low Voltage Differential True Clock Input. 7CLKINCI Complementary Clock Input. Low Voltage Differential Complementary Clock Input. 22 FBINC I Feedback Complementary Clock Input. Differential Input Connect to FBOUTC for accessing the PLL. 23 FBINT I Feedback True Clock Input. Differential Input Connect to FBOUTT for accessing the PLL. 3,12,17,26 YT(0:3) O True Clock Outputs. Differential Outputs. 2,13,16,27 YC(0:3) O Complementary Clock Outputs. Differential Outputs. 19 FBOUTT O Feedback True Clock Output. Differential Outputs. Connect to FBINT for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 20 FBOUTC O Feedback Complementary Clock Output. Differential Outputs. Connect to FBINC for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. 24 PWRDWN I Control input to turn device in the power-down mode. 4,8,11,18,21,25 VDDQ 2.5V Power Supply for Output Clock Buffers.2.5V Nominal. 9AVDD 2.5V Power Supply for PLL. 2.5V Nominal. 1,5,14,15,28 GND Ground 10 AGND Analog Ground. 2.5V Analog Ground. connecting the feedback output to the feedback input the Zero-delay Buffer propagation delay through the device is eliminated. The PLL When used as a zero-delay buffer the CY2SSTV855 will likely works to align the output edge with the input reference edge be in a nested clock tree application. For these applications thus producing a near zero delay. The reference frequency the CY2SSTV855 offers a differential clock input pair as a PLL affects the static phase offset of the PLL and thus the relative reference. The CY2SSTV855 then can lock onto the reference delay between the inputs and outputs. and translate with near zero delay to low-skew outputs. For When AVDD is strapped LOW, the PLL is turned off and normal operation, the external feedback differential input, bypassed for test purposes. FBINT/C, is connected to the feedback output, FBOUTT/C. By Function Table Inputs Outputs AVDD PWRDWN CLKINT CLKINC YT(0:3) YC(0:3) FBOUTT FBOUTC PLL H GND H L L H L H BYPASSED/OFF GND H H L H L H L BYPASSED/OFF 2.5V H L H L H L H On 2.5V H H L H L H L On 2.5V X < 20 MHz < 20 MHz Hi-Z Hi-Z Hi-Z Hi-Z Off Notes: 1. PU = internal pull-up. 2. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (< 0.2). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces........................ Document : 38-07459 Rev. *F Page 2 of 6