CY2SSTV857-32
CY2SSTV857-32
Differential Clock Buffer/Driver DDR400/PC3200-Compliant
Features Description
Operating frequency: 60 MHz to 230 MHz The CY2SSTV857-32 is a high-performance, low-skew,
low-jitter zero-delay buffer designed to distribute differential
Supports 400 MHz DDR SDRAM
clocks in high-speed applications. The CY2SSTV857-32
10 differential outputs from one differential input
generates ten differential pair clock outputs from one differ-
ential pair clock input. In addition, the CY2SSTV857-32
Spread-Spectrum-compatible
features differential feedback clock outpts and inputs. This
Low jitter (cycle-to-cycle): < 75
allows the CY2SSTV857-32 to be used as a zero delay buffer.
Very low skew: < 100 ps
When used as a zero delay buffer in nested clock trees, the
Power management control input CY2SSTV857-32 locks onto the input reference and translates
with near-zero delay to low-skew outputs.
High-impedance outputs when input clock < 20 MHz
2.6V operation
Pin-compatible with CDC857-2 and -3
48-pin TSSOP and 40 QFN package
Industrial temperature of 40C to 85C
Conforms to JEDEC DDR specification
Block Diagram Pin Configuration
VSS 1 48 VSS
3
Y0
Y0# 2 47 Y5#
2
Y0#
Y0 3 46 Y5
5
Y1
37
Test and
PD 6 VDDQ 4 45 VDDQ
Y1#
Powerdown
Y1 5 44 Y6
10
16
Logic
Y2
AVDD
9 Y1# 6 43 Y6#
Y2#
VSS 7 42 VSS
20
Y3
VSS 8 41 VSS
19
Y3#
Y2# 9 40 Y7#
22
Y4
Y2 10 39 Y7
23
Y4#
VDDQ 11 38 VDDQ
46
Y5
VDDQ 12 37 PD#
47
Y5#
CLK 13 36 FBIN
44
Y6
CLK# 14 35 FBIN#
43
Y6#
VDDQ 15 34 VDDQ
13
CLK 39
AVDD 16 33 FBOUT#
Y7
14
CLK# 40
Y7#
AVSS 17 32 FBOUT
PLL
29
36 Y8 VSS 18 31 VSS
FBIN
35 30
Y8#
FBIN# Y3# 19 30 Y8#
27 Y3 20 29 Y8
Y9
26
VDDQ 21 28 VDDQ
Y9#
Y4 22 27 Y9
32 Y4# 23 26 Y9#
FBOUT
33
VSS 24 25 VSS
FBOUT#
.......................... Document #: 38-07557 Rev. *E Page 1 of 8
400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com
CY2SSTV857
40 QFN Package
40 37 36 35
39 38 34 33 32 31
30 Y7#
VSS 1
Y7
29
Y2# 2
28 VDDQ
Y2 3
PD#
VDDQ 27
4 40 QFN
FBIN
CLK CY2SSTV857-32 26
5
25 FBIN#
CLK# 6
VDDQ
VDDQ 24
7
VDDQ
AVDD 23
8
22
9 FBOUT#
AVSS
VSS 10 21 FBOUT
11 14 15 16
12 13 17 18 19 20
Pin Description
Pin # Pin # Electrical
[1]
48 TSSOP 40 QFN Pin Name I/O Pin Description Characteristics
13, 14 5,6 CLK, CLK# I Differential Clock Input. LV Differential Input
35 25 FBIN# I Feedback Clock Input. Connect to FBOUT# for Differential Input
accessing the PLL.
36 26 FBIN I Feedback Clock Input. Connect to FBOUT for
accessing the PLL.
3, 5, 10, 20, 22 37,39,3,12,14 Y(0:4) O Clock Outputs. Differential Outputs
2, 6, 9, 19, 23 36,40,2,11,15 Y#(0:4) O Clock Outputs.
27, 29, 39, 44, 46 17,19,29,32,34 Y(9:5) O Clock Outputs. Differential Outputs
26, 30, 40, 43, 47 16,20,30,31,35 Y#(9:5) O Clock Outputs.
32 21 FBOUT O Feedback Clock Output. Connect to FBIN for Differential Outputs
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
33 22 FBOUT# O Feedback Clock Output. Connect to FBIN# for
normal operation. A bypass delay capacitor at
this output will control Input Reference/Output
Clocks phase relationships.
37 27 PD# I Power Down Input. When PD# is set HIGH, all
Q and Q# outputs are enabled and switch at the
same frequency as CLK. When set LOW, all Q
and Q# outputs are disabled Hi-Z and the PLL
is powered down.
4, 11,12,15, 21, 4,7,13,18,23,24, VDDQ 2.6V Power Supply for Output Clock Buffers.2.6V Nominal
28, 34, 38, 45 28,33,38
16 8 AVDD 2.6V Power Supply for PLL. When VDDA is at 2.6V Nominal
GND, PLL is bypassed and CLK is buffered
directly to the device outputs. During disable
(PD# = 0), the PLL is powered down.
1, 7, 8, 18, 24, 25, 1,10 VSS Common Ground. 0.0V Ground
31, 41, 42, 48
17 9 AVSS Analog Ground.0.0V Analog
Ground
Note:
1. A bypass capacitor (0.1 F) should be placed as close as possible to each positive power pin (<0.2). If these bypass capacitors are not close to the pins, their
high-frequency filtering characteristic will be cancelled by the lead inductance of the traces.
..........................Document #: 38-07557 Rev. *E Page 2 of 8
Y1#
Y3#
y3 Y1
VDDQ
VDDQ
Y4
Y0
Y4#
Y0#
Y9#
Y5#
Y9
Y5
VDDQ
VDDQ
Y8
Y6
Y8#
Y6#