CY7B9930V/CY7B9940V
RoboClockII Junior
High-Speed Multifrequency
PLL Clock Buffer
High-Speed Multifrequency PLL Clock Buffer
Features Functional Description
12100 MHz (CY7B9930V), or 24200 MHz (CY7B9940V) The CY7B9930V and CY7B9940V High-Speed Multifrequency
input/output operation PLL Clock Buffers offer user-selectable control over system
clock functions. This multiple output clock driver provides the
Matched pair output skew < 200 ps
system integrator with functions necessary to optimize the timing
of high performance computer or communication systems.
Zero input-to-output delay
Ten configurable outputs can each drive terminated transmission
10 LVTTL 50% duty-cycle outputs capable of driving 50
lines with impedances as low as 50 while delivering minimal and
terminated lines
specified output skews at LVTTL levels. The outputs are arranged
Commercial temperature range with eight outputs at 200 MHz in three banks. The FB feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12. Any one of
Industrial temperature range with eight outputs at 200 MHz
these ten outputs can be connected to the feedback input as well
as driving other inputs.
3.3V LVTTL/LV differential (LVPECL), fault-tolerant and hot
insertable reference inputs
Selectable reference input is a fault tolerance feature that allows
smooth change over to secondary clock source, when the
Multiply ratios of (16, 8, 10, 12)
primary clock source is not in operation. The reference inputs are
Operation up to 12x input frequency configurable to accommodate both LVTTL or differential
(LVPECL) inputs. The completely integrated PLL reduces jitter
Individual output bank disable for aggressive power
and simplifies board layout.
management and EMI reduction
For a complete list of related documentation, click here.
Output high impedance option for testing purposes
Fully integrated PLL with lock indicator
Low cycle-to-cycle jitter (<100 ps peak-peak)
Single 3.3V 10% supply
44-pin TQFP package
Logic Block Diagram
FBKA
LOCK
Control Logic
Phase
VCO
Divide
Filter
Freq.
REFA+ Generator
Detector
REFA
REFB+
FS
3
REFB
Output_Mode
3
REFSEL
QFA0
Divide
3
Feedback Bank FBDS0
QFA1
Matrix
FBDS1 3
2QA0
2QA1
Bank 2
2QB0
2QB1
DIS2
1QA0
1QA1
Bank 1
1QB0
1QB1
DIS1
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-07271 Rev. *J Revised May 3, 2016CY7B9930V/CY7B9940V
RoboClockII Junior
Contents
Logic Block Diagram Description ......................................3 Switching Characteristics ...................................................10
Phase Frequency Detector and Filter .............................3
AC Timing Diagrams ...........................................................11
VCO, Control Logic, and Divide Generator ....................3
Ordering Information ...........................................................12
Divide Matrix ...................................................................3
Ordering Code Definitions ..............................................12
Output Disable Description .............................................3
Package Diagram .................................................................13
Lock Detect Output Description ......................................4
Acronyms .............................................................................14
Factory Test Mode Description ......................................4
Document Conventions ......................................................14
Pin Configuration ................................................................5
Units of Measure ............................................................14
Pin Definitions .....................................................................6
Document History Page ......................................................15
Absolute Maximum Conditions ..........................................7
Sales, Solutions, and Legal Information ...........................16
Operating Range ..................................................................7
Worldwide Sales and Design Support ............................16
Electrical Characteristics ....................................................7
Products .........................................................................16
Capacitance .........................................................................9
PSoCSolutions ............................................................16
Thermal Resistance .............................................................9 Cypress Developer Community ......................................16
Technical Support ..........................................................16
AC Test Loads and Waveforms ..........................................9
Document Number: 38-07271 Rev. *J Page 2 of 16