CY2VC521-2
Low Noise LVDS Clock Generator with VCXO
Features Description
Output: 216 MHz Output Clock The CY2VC521-2 is a PLL-based clock generator with VCXO
control and very low output jitter. When the user connects a
Input: External 27 MHz Crystal
fundamental mode 27 MHz crystal, this device generates a
216 MHz output clock. The CY2VC521-2 has one LVDS output
Differential LVDS Output with 2x Drive to Drive Two Loads
pair tuned to drive two standard LVDS loads and operates from
VCXO gives 230 ppm Minimum Pull Range
a single 3.3V power supply.
Low RMS Phase Jitter (12 kHz20 MHz): 1.3 ps Typical The VIN pin is an analog input that enables the user to pull the
output frequency. The pullability range is at least 230 ppm (115
Low Phase Noise
ppm).
Fully Integrated Low Noise Phase Locked Loop (PLL)
Unlike conventional VCXO designs, the output frequency
adjustment is not achieved by adjusting capacitance at the pins
Excellent Voltage-to-Frequency Linearity
of the crystal. Instead, a proprietary PLL design is used. This
Supply Voltage: 3.3V permits the use of a standard 27 MHz crystal. A special pullable
crystal is neither required nore recommended.
Pb-free 16-Pin TSSOP Package
Logic Block Diagram
XIN
External
CLK
CRYSTAL LOW-NOISE
27 MHz
OSCILLATOR PLL
CLK#
Crystal
XOUT
VIN
SEL
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 001-15599 Rev. *E Revised May 14, 2010
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CY2VC521-2
Pinout
Figure 1. Pin Diagram - 16-Pin TSSOP
XIN 1 16 XOUT
VDD 2 15 NC
VDD 314 CLK
VDD 4 13 CLK#
VIN 5 12 VSS
VSS 611 NC
VSS 7 10 VDD
VSS 89 SEL
Table 1. Pin Definitions - 16-Pin TSSOP
Pin Name Type Description
1 XIN Crystal Oscillator Input: Connect a 27 MHz crystal between XIN and XOUT
16 XOUT Crystal Oscillator Output: Connect a 27 MHz crystal between XIN and XOUT
5 VIN Analog Input VCXO Control Voltage: VIN has a positive control slope, meaning that increasing the
voltage on VIN causes the output frequency to increase. The nominal output frequency
is determined when VIN = 1.65V
13, 14 CLK#, CLK LVDS Output Differential output clock
9 SEL CMOS Input Select: Hold this pin LOW for normal operation
11, 15 NC No Connect: NC pins are not connected to the die
2, 3, 4, 10 VDD 3.3V power supply
6, 7, 8, 12 VSS Ground
Document Number: 001-15599 Rev. *E Page 2 of 9
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