74HC4046APW,112 Nexperia

74HC4046A 74HCT4046A Phase-locked loop with VCO Rev. 4 6 August 2019 Product data sheet 1. General description The 74HC4046A 74HCT4046A is a high-speed Si-gate CMOS device. It is specified in compliance with JEDEC standard no 7A. 2. Features and benefits Low power consumption VCO-Inhibit control for ON/OFF keying and for low standby power consumption Center frequency up to 17 MHz (typical) at V = 4.5 V CC Choice of three phase comparators: PC1: EXCLUSIVE-OR PC2: Edge-triggered J-K flip-flop PC3: Edge-triggered RS flip-flop Excellent Voltage Controlled Oscillator (VCO) linearity Low frequency drift with supply voltage and temperature variations Operating power supply voltage range: VCO section 3.0 V to 6.0 V Digital section 2.0 V to 6.0 V Zero voltage offset due to operational amplifier buffering ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V 3. Applications FM modulation and demodulation Frequency synthesis and multiplication Frequency discrimination Tone decoding Data synchronization and conditioning Voltage-to-frequency conversion Motor-speed controlNexperia 74HC4046A 74HCT4046A Phase-locked loop with VCO 4. Ordering information Table 1. Ordering information Type number Package Name Description Version 74HC4046AD SO16 plastic small outline package 16 leads body width 3.9 mm SOT109-1 74HCT4046AD 74HC4046ADB SSOP16 plastic shrink small outline package 16 leads body width 5.3 mm SOT338-1 74HCT4046ADB 74HC4046APW TSSOP16 plastic thin shrink small outline package 16 leads body width 4.4 mm SOT403-1 5. Block diagram C1 6 7 4 3 14 C1A C1B VCO OUT COMP IN SIG IN 4046A PHASE R2 12 PC1 OUT 2 COMPARATOR 1 R2 VCO PC2 OUT 13 PHASE R3 R1 11 COMPARATOR PCP OUT 1 2 R1 R4 PHASE PC3 OUT 15 COMPARATOR C2 3 5 10 9 INH DEM OUT VCO IN R S aaa-020201 Fig. 1. Block diagram 74HC HCT4046A All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2019. All rights reserved Product data sheet Rev. 4 6 August 2019 2 / 36