DATASHEET FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 9DB433 Description Features The 9DB433 zero-delay buffer supports PCIe Gen3 3 selectable SMBus addresses multiple devices can requirements, while being backwards compatible to PCIe share the same SMBus segment Gen2 and Gen1. The 9DB433 is driven by a differential OE pins suitable for Express Card applications SRC output pair from an IDT 932S421 or 932SQ420 or PLL or bypass mode PLL can dejitter incoming clock equivalent main clock generator. Selectable PLL bandwidth minimizes jitter peaking in downstream PLLs Typical Applications Spread spectrum compatible tracks spreading input 4 output PCIe Gen13 zero-delay/fanout buffer clock for low EMI SMBus interface unused outputs can be disabled Key Specifications Supports undriven differential outputs in Power Down Output cycle-cycle jitter <50ps mode for power management Output to Output skew <50ps Output Features Phase jitter: PCIe Gen3 <1.0ps rms 4 0.7V current-mode differential HCSL output pairs Supports zero delay buffer mode and fanout mode Selectable bandwidth 50110MHz operation in PLL mode 5166MHz operation in Bypass mode Block Diagram 2 OE(6,1) SPREAD SRC IN COMPATIBLE PLL SRC IN 4 M STOP U DIF(6,5,2,1) LOGIC X PD CONTROL BYP LOBW HIBW LOGIC SMBDAT SMBCLK IREF IDT FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 1 9DB433 MAY 25, 20189DB433 FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 Pin Configuration VDDR 1 28 VDDA SRC IN 2 27 GNDA SRC IN 3 26 IREF GND 4 25 PD VDD 5 24 VDD DIF 1 6 23 DIF 6 DIF 1 7 22 DIF 6 OE1 8 21 OE6 DIF 2 9 20 DIF 5 DIF 2 10 19 DIF 5 VDD 11 18 VDD BYP HIBW LOBW 12 17 SMB ADR tri SMBCLK 13 16 VDD SMBDAT 14 15 GND Notes: Highlighted Pins are the differences between 9DB403 and 9DB433. Pin 12 and Pin 17 are latched on power up. Please make sure that the power supply to the pullup/pulldown resistors ramps at the same time as the main supply to the chip. SMBus Address Selection and Readback SMB ADR tri Address Low DA/DB Mid DC/DD High D8/D9 PLL Operating Mode Readback Table BYP LOBW HIBW MODE Byte0, bit 3 Byte 0 bit 1 Low Bypass 0 0 Mid PLL 100M Hi BW 1 0 High PLL 100M Low BW 0 1 Power Groups Tri-Level Input Logic Pins Pin Number State of Pin Voltage Description Low <0.8V VDD GND Mid 1.2<Vin<1.8V 1 4 SRC IN/SRC IN High Vin > 2.0V 5,11,18, 24 4 DIF(1,2,5,6) 16 15 DIGITAL VDD/GND 28 27 Analog VDD/GND for PLL in IREF For best results, treat pin 1 as analog VDD. IDT FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN13 2 9DB433 MAY 25, 2018 9DB433