CY7B991V 3.3 V RoboClock Low Voltage Programmable Skew Clock Buffer 3.3 V RoboClock Low Voltage Programmable Skew Clock Buffer Features Functional Description All output pair skew <100 ps typical (250 ps max) The CY7B991V 3.3 V RoboClock low-voltage programmable skew clock buffer (LVPSCB) offers user-selectable control over 3.75 MHz to 80 MHz output operation system clock functions. These multiple output clock drivers provide the system integrator with functions necessary to User-selectable output functions: optimize the timing of high-performance computer systems. Selectable skew up to 18 ns Each of the eight individual drivers arranged in four pairs of Inverted and non-inverted user controllable outputs can drive terminated transmission Operation at one-half and one-quarter input frequency lines with impedances as low as 50 . This delivers minimal Operation at 2 and 4 input frequency (input as low as output skews and full-swing logic levels (LVTTL). 3.75 MHz) Each output is hardwired to one of nine delay or function Zero input to output delay configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency, with outputs able to skew up to 6 50% duty cycle outputs time units from their nominal zero skew position. The Low-voltage transistor-transistor logic (LVTTL) outputs drive completely-integrated phase-locked loop (PLL) allows external 50 terminated lines load and transmission line delay effects to be canceled. When this zero delay capability of the LVPSCB is combined with the Operates from a single 3.3 V supply selectable output skew functions, the user can create output-to-output delays of up to 12 time units. Low operating current Divide-by-two and divide-by-four output functions are provided 32-pin plastic leaded chip carrier (PLCC) package for additional flexibility in designing complex clock systems. Low cycle-to-cycle jitter (100 ps typical) When combined with the internal PLL, these divide functions enable distribution of a low frequency clock that is multiplied by two or four at the clock destination. This feature minimizes clock distribution difficulty, allowing maximum system clock speed and flexibility. For a complete list of related resources, click here. Logic Block Diagram TEST PHASE FB VCO AND FREQ FILTER TIME UNIT DET REF GENERATOR FS 4Q0 4F0 4F1 SELECT 4Q1 INPUTS (THREE SKEW LEVEL) 3Q0 3F0 3F1 3Q1 SELECT 2Q0 2F0 MATRIX 2F1 2Q1 1Q0 1F0 1F1 1Q1 Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600 Document Number: 38-07141 Rev. *M Revised January 3, 2018 CY7B991V Contents Pinouts ..............................................................................3 Switching Characteristics (-7 Option) ..........................13 Pin Definitions ..................................................................3 AC Timing Diagrams ...................................................... 14 Block Diagram Description ..............................................4 Ordering Information ...................................................... 15 Phase Frequency Detector and Filter ..........................4 Package Diagram ............................................................ 16 VCO and Time Unit Generator ....................................4 Acronyms ........................................................................ 17 Skew Select Matrix ......................................................4 Document Conventions ................................................. 17 Test Mode ..........................................................................5 Units of Measure ....................................................... 17 Operational Mode Descriptions ......................................6 Document History Page ................................................. 18 Maximum Ratings .............................................................9 Sales, Solutions, and Legal Information ...................... 20 Operating Range ...............................................................9 Worldwide Sales and Design Support ....................... 20 Electrical Characteristics .................................................9 Products .................................................................... 20 Capacitance ....................................................................10 PSoC Solutions ...................................................... 20 Thermal Resistance ........................................................10 Cypress Developer Community ................................. 20 AC Test Loads and Waveforms .....................................10 Technical Support ..................................................... 20 Switching Characteristics (-2 option) ...........................11 Switching Characteristics (-5 Option) ..........................12 Document Number: 38-07141 Rev. *M Page 2 of 20