EFM8SB20F64G-A-QFN24 Silicon Labs

EFM8 Sleepy Bee Family EFM8SB2 Reference Manual The EFM8SB2, part of the Sleepy Bee family of MCUs, is the ENERGY FRIENDLY FEATURES worlds most energy friendly 8-bit microcontrollers with a compre- Lowest MCU sleep current with supply hensive feature set in small packages. brownout detection (50 nA) These devices offer lowest power consumption by combining innovative low energy tech- Lowest MCU active current with these features (170 A / MHz at 24.5 MHz clock niques and short wakeup times from energy saving modes into small packages, making rate) them well-suited for any battery operated applications. With an efficient 8051 core, 6-bit current reference, and precision analog, the EFM8SB2 family is also optimal for embed- Lowest MCU sleep current using internal RTC operating and supply brownout ded applications. detection (<300 nA) EFM8SB2 applications include the following: Ultra-fast wake up for digital and analog peripherals (< 2 s) Battery-operated consumer electronics Hand-held devices Integrated low drop out (LDO) voltage Sensor interfaces Industrial controls regulator to maintain ultra-low active current at all voltages Core / Memory Clock Management Energy Management Low Power 20 CIP-51 8051 Core External Internal LDO MHz RC Power-On Reset Oscillator Regulator (25 MHz) Oscillator Flash Program High Frequency RAM Memory Debug Interface External 32 kHz Memory 24.5 MHz RC Brown-Out Detector (4352 bytes) with C2 RTC Oscillator (up to 64 KB) Oscillator 8-bit SFR bus Serial Interfaces I/O Ports Timers and Triggers Analog Interfaces Security Comparator 0 16/32-bit CRC External Timers ADC UART 2 x SPI Pin Reset PCA/PWM Interrupts 0/1/2/3 Internal Voltage Comparator 1 Reference General Watchdog Real Time 2 I C / SMBus Pin Wakeup Purpose I/O Timer Clock Internal Current Reference Lowest power mode with peripheral operational: Normal Idle Suspend Sleep silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 EFM8SB2 Reference Manual System Overview 1. System Overview 1.1 Introduction Port I/O Configuration CIP-51 8051 Controller Power On Core Reset/PMU Digital Peripherals Wake 64/32/16 KB ISP Flash UART Program Memory Reset Timers 0, Port 0 256 Byte SRAM P0.n 1, 2, 3 C2CK/RSTb Drivers Debug / Programming Priority 4096 Byte XRAM Hardware Crossbar PCA/WDT Decoder Port 1 P1.n C2D SMBus Drivers SPI 0,1 Power Net VDD VREG CRC Analog Digital SYSCLK Port 2 Power Power Crossbar Control P2.n Drivers GND System Clock SFR Configuration Bus External Memory Interface Control Precision 24.5 MHz Address Oscillator Data Low Power Analog Peripherals 20 MHz Oscillator Comparators External Internal XTAL1 External + + Oscillator VREF - VREF VDD - XTAL2 Circuit VREF 10-bit Temp 6-bit IREF0 300ksps Sensor IREF XTAL3 RTC ADC Oscillator XTAL4 GND Figure 1.1. Detailed EFM8SB2 Block Diagram silabs.com Smart. Connected. Energy-friendly. Rev. 0.1 1 AMUX