SI3402-EVB Silicon Labs

Si3402B-EVB NON-ISOLATED EVALUATION BOARD FOR THE Si3402B 1. Description The Si3402B non-isolated evaluation board (Si3402B-EVB Rev 2) is a reference design for a power supply in a Power over Ethernet (PoE) Powered Device (PD) application. The Si3402B is described more completely in the data sheet and application notes. This document describes the evaluation board. An evaluation board demonstrating the isolated application is described in the Si3402B-ISO-EVB users guide. 2. Si3402B Board Interface Ethernet data and power are applied to the board through the RJ45 connector (J1). The board itself has no Ethernet data transmission functionality, but, as a convenience, the Ethernet transformer secondary is brought out to the test points. Power may be applied in the following ways: Connecting a dc source to pins 1, 2 and 3, 6 of the Ethernet cable (either polarity) Connecting a dc source to pins 4, 5 and 7, 8 of the Ethernet cable (either polarity) Using an IEEE 802.3-2015-compliant, PoE-capable PSE, such as Trendnet TPE-1020WS The Si3402B-EVB board schematics and layout are shown in Figures 1 through 6. The dc output is at connectors J11(+) and J12(). Boards are generally shipped configured to produce +5 V output voltage but can be configured for +3.3 V or other output voltages by changing resistors R5 and R6. Refer to AN956: Using the Si3402B PoE PD Controller in Isolated and Non-Isolated Designs for more information. The preconfigured Class 3 signature can also be modified according to Table 3 in AN956. The D8D15 Schottky type diode bridge bypass is recommended only for higher power levels (Class 3 operation). For lower power levels, such as Class 1 and Class 2, the diodes can be removed. When the Si3402B is used in external diode bridge configuration, it requires that at least one pair of the CTx and SPx pins be connected to the PoE voltage input terminals (to the input of the external bridge). Rev. 1.1 4/16 Copyright 2016 by Silicon Laboratories Si3402B-EVBSi3402B-EVB 2 Rev. 1.1 R1 330 Vpos is a EMI and ESD plane. Use top layer. R2 5V 49.9K RJ-45 J1 Vpos BND POST J11 + D1 1 + C5 R9 MX0+ TP2 NI PDS5100 2 560uF TP3 NI CT 100 3 C20 MX0- TP4 NI J12 NI BND POST 4 L1 33uH 30 Ohm TP5 NI MX1+ 5 CT/MX1- TP6 NI 6 FB1 MX1- FB 7 PWR1 Connect inductor and Vss output filter caps C7 together minimizing 1nF area of return loop and then connect At least one pair of CT1/CT2 or to output ground plane. U1 SP1/SP2 should be connected. C19 C8 NI R7 0.1uF 47K 1 EROUT 14 CT1 2 NC 13 CT2 Si3402B 3 Vdd 12 Vpos 4 NC 11 SP1 L5 330 Ohm L4 330 Ohm L3 330 Ohm L2 330 Ohm NI = Not Installed Vneg Optional bypass diodes for >7W applications are in parallel with C10-C17 Vneg Vneg is a thermal plane as wel as ESD and EMI. Use thermal vias to at least 1 inch square plane on backside 1 to 1.2mm pitch 0.3 to 0.33mm diameter. Figure 1. Si3402B Schematic5 V, Class 3 PD 11 K2 PWR5 LED K2 10 A2 PWR4 LED A2 9 K1 PWR3 LED K1 8 A1 PWR2 LED A1 SS2150 D15 SS2150 D8 1nF C10 1nF C17 SS2150 D14 SS2150 D9 1nF C11 1nF C16 SS2150 D13 SS2150 D10 1nF C12 1nF C15 SS2150 D12 SS2150 D11 1nF C13 1nF C14 C18 0.1uF 1uF C1 12uF C2 10 15 1uF C3 SP2 Vssa 9 16 Vneg NC 1uF C4 8 17 RCL NC R3 48.7 7 18 SWO HSO SWO 6 19 RDET VSS2 R4 24.3k 5 20 nploss FB R6 8.66K R5 3.24K C6 22uF