Si53119-A03A 19-OUTPUT PCIE GEN 3 BUFFER Features Nineteen 0.7 V low-power, push- Integrated termination resistors pull HCSL PCIe Gen 3 outputs supporting 85 transmission lines 100 MHz /133 MHz PLL operation, supports PCIe and PLL or bypass mode QPI Spread spectrum tolerable PLL bandwidth SW SMBUS 1.05 to 3.3 V I/O supply voltage programming overrides the latch 50 ps output-to-output skew value from HW pin 50 ps cyc-cyc jitter (PLL mode) Ordering Information: 9 selectable SMBUS addresses See page 31. Low phase jitter (Intel QPI, PCIe SMBus address configurable to Gen 1/Gen 2/Gen 3 common allow multiple buffers in a single clock compliant) control network 3.3 V supply Pin Assignments 100 ps input-to-output delay voltage operation Gen3 SRNS Compliant Separate VDDIO for outputs Extended Temperature: DIF 12 VDDA 1 54 53 DIF 12 40 to 85 C GNDA 2 100M 133M 3 52 VDD IO GND HBW BYPASS LBW 4 51 DIF 11 72-pin QFN PWRGD / PWRDN 5 50 GND 6 49 DIF 11 VDDR 7 48 DIF 10 DIF 10 For variations of this device, CLK IN 8 47 Si53119 CLK IN 9 GND 46 VDD SA 0 10 45 contact Skyworks Solutions SDA 11 44 DIF 9 SCL DIF 9 12 43 SA 1 13 42 DIF 8 FBOUT NC 14 41 DIF 8 FBOUT NC VDD IO 15 40 Applications 16 GND GND 39 DIF 0 17 38 DIF 7 DIF 0 18 37 DIF 7 Server Data center Storage Enterprise switches and routers Patents pending Description The Si53119-A03A is a 19-output, low-power HCSL differential clock buf- fer that meets all of the performance requirements of the Intel DB1200ZL specification. To reduce board space and bill of material cost, the device fully integrates all external resistors, supporting 85 transmission lines. It is optimized for distributing reference clocks for Intel QuickPath Inter- connect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz operation. Each 2 differential output can be enabled through I C for maximum flexibility and power savings. Measuring PCIe clock jitter is quick and easy with the Skyworks Solutions PCIe Clock Jitter Tool. Download it for free at Si53119-A03A Functional Block Diagram FB OUT SSC Compatible DIF 18:0 CLK IN PLL CLK IN 100M 133 HBW BYPASS LBW SA 0 Control SA 1 Logic PWRGD / PWRDN SDA SCL 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 1.1 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021