Si53152 PCI-EXPRESS GEN 1, GEN 2, GEN 3, AND GEN 4 FANOUT BUFFER Features PCI-Express Gen 1, Gen 2, Gen 3, Dedicated output enable pin for and Gen 4 common clock each clock compliant Two PCI-Express buffered clock Supports Serial ATA (SATA) at outputs 100 MHz Supports LVDS outputs 100210 MHz operation 2 I C support with readback Low power, push pull, differential capabilities output buffers Extended temperature: Internal termination for maximum 40 to 85 C integration 3.3 V Power supply Ordering Information: 24-pin QFN package See page 17 Applications Network attached storage Wireless access point Pin Assignments Multi-function Printer Routers Description 24 23 22 21 20 19 OE DIFF1* VDD 1 18 The Si53152 is a spread spectrum tolerant PCIe clock buffer that can source 17 VDD 2 NC two PCIe clocks simultaneously. The device has two hardware output enable 16 VDD 3 DIFF1 inputs for enabling the respective differential outputs on the fly. The device 25 GND 15 DIFF1 2 2 4 VSS also features output enable control through I C communication. I C 14 DIFF0 OE DIFF0* 5 programmability is also available to dynamically control skew, edge rate and 13 DIFF0 VDD 6 amplitude on the true, compliment, or both differential signals on the clock 7 8 9 10 11 12 outputs. This control feature enables optimal signal integrity as well as optimal EMI signature on the clock outputs. Measuring PCIe clock jitter is *Note: Internal 100 kohm pull-up. quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it for free at www.silabs.com/pcie-learningcenter. Patents pending Functional Block Diagram DIFF0 DIFFIN DIFFIN DIFF1 Control & Memory SCLK SDATA Control RAM OE 1:0 Rev. 1.2 4/16 Copyright 2016 by Silicon Laboratories Si53152 VSS NC DIFFIN NC DIFFIN NC VDD NC SDATA NC SCLK VDDSi53152 2 Rev. 1.2