Si5325 P-PROGRAMMABLE PRECISION CLOCK MULTIPLIER Features Not recommended for new Dual clock outputs with designs. For alternatives, see the selectable signal format Si533x family of products. (LVPECL, LVDS, CML, CMOS) Generates frequencies from Support for ITU G.709 and 2 kHz to 945 MHz and select custom FEC ratios (255/238, frequencies to 1.4 GHz from an 255/237, 255/236) input frequency of 10 to 710 MHz LOS, FOS alarm outputs Low jitter clock outputs with jitter 2 I C or SPI programmable generation as low as 0.5 ps rms On-chip voltage regulator for (12kHz20MHz) 1.8 5%, 2.5 or 3.3 V 10% Integrated loop filter with Ordering Information: operation selectable loop bandwidth See page 56. Small size: 6 x 6 mm 36-lead (150 kHz to 2 MHz) QFN Dual clock inputs w/manual or Pb-free, ROHS compliant automatically controlled Pin Assignments switching Applications SONET/SDH OC-48/STM-16 and Optical modules OC-192/STM-64 36 35 34 33 32 31 30 29 28 Wireless basestations RST 1 27 SDI line cards Data converter clocking NC 2 26 A2 SS GbE/10GbE, 1/2/4/8/10GFC line xDSL INT C1B 3 25 A1 cards SONET/SDH + PDH clock synthesis C2B 4 24 A0 GND ITU G.709 and custom FEC line VDD 5 23 SDA SDO Test and measurement Pad GND 6 22 SCL cards NC 7 21 CS CA GND 8 20 GND Description 9 GND NC 19 10 11 12 13 14 15 16 17 18 The Si5325 is a low jitter, precision clock multiplier for applications requiring clock multiplication without jitter attenuation. The Si5325 accepts dual clock inputs ranging from 10 to 710 MHz and generates two clock outputs ranging from 2 kHz to 945 MHz and select frequencies to 1.4 GHz. The two outputs are divided down separately from a common source. The device provides frequency translation combinations across this operating range. The Si5325 input clock frequency and 2 clock multiplication ratio are programmable through an I C or SPI interface. The Si5325 is based on Silicon Laboratories 3rd-generation DSPLL technology, which provides frequency synthesis in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable. Operating from a single 1.8, 2.5, or 3.3V supply, the Si5325 is ideal for providing clock multiplication in high performance timing applications. Rev. 1.0 9/14 Copyright 2014 by Silicon Laboratories Si5325 VDD CMODE VDD CKOUT2+ CLKIN2+ CKOUT2 CLKIN2 NC NC VDD VDD GND CLKIN1+ NC CLKIN1 CLKOUT1 NC CLKOUT1+Si5325 Functional Block Diagram N31 CKIN1 NC1 LS CKOUT1 CKIN2 N32 DSPLL N1 HS NC2 LS CKOUT2 N2 VDD (1.8, 2.5, or 3.3 V) Alarms Signal Detect Control GND 2 I C/SPI Port Clock Select Device Interrupt 2 Rev. 1.0