Si5323 PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER/JITTER ATTENUATOR Features Pin-selectable output frequencies Dual clock outputs with selectable ranging from 8 kHz708 MHz signal format (LVPECL, LVDS, CML, CMOS) Ultra-low jitter clock outputs as low as 250 fs rms (12 kHz20 MHz) Support for ITU G.709 FEC ratios 270 fs rms (50 kHz80 MHz) (255/238, 255/237, 255/236) Integrated loop filter with selectable LOL, LOS alarm outputs loop bandwidth (60 Hz8.4 kHz) Pin-controlled output phase adjust Meets ITU-T G.8251 and Telcordia Single supply 1.8 5%, 2.5 or 3.3 V OC-192 GR-253-CORE jitter 10% operation with high PSRR Ordering Information: specifications On-chip voltage regulator See page 33. Hitless input clock switching with Small size: 6 x 6 mm 36-lead QFN phase build-out and digital hold Applications Pin Assignments SONET/SDH OC-48/STM-16 and ITU G.709 line cards OC-192/STM-64 line cards Optical modules GbE/10GbE, 1/2/4/8/10GFC line cards Test and measurement Synchronous Ethernet 36 35 34 33 32 31 30 29 28 1 27 FRQSEL3 RST Description 2 26 FRQTBL FRQSEL2 C1B 3 25 FRQSEL1 4 24 C2B FRQSEL0 The Si5323 is a jitter-attenuating precision clock multiplier for high-speed GND 5 23 VDD BWSEL1 Pad communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre XA 6 22 BWSEL0 XB 7 21 CS CA Channel. The Si5323 accepts dual clock inputs ranging from 8 kHz to 707 MHz GND 8 20 INC and generates two equal frequency-multiplied clock outputs ranging from 8 kHz to AUTOSEL 9 DEC 19 10 11 12 13 14 15 16 17 18 1050 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. The Si5323 is based on Silicon Laboratories 3rd-generation DSPLL technology, which provides any-frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or 3.3 V supply, the Si5323 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications. Functional Block Diagram Xtal or Refclock CKOUT1 CKIN1 Signal Format DSPLL CKOUT2 CKIN2 Disable/BYPASS Loss of Signal Control Signal Detect Loss of Lock VDD (1.8, 2.5, or 3.3 V) GND Frequency Select Manual//Auto Switch Bandwidth Select Clock Select Rate Select Skew Control Rev. 1.0 1/11 Copyright 2011 by Silicon Laboratories Si5323 VDD NC RATE0 CKOUT2+ CKIN2+ CKOUT2 CKIN2 SFOUT0 DBL2 BY VDD RATE1 GND CKIN1+ SFOUT1 CKIN1 CKOUT1 LOL CKOUT1+Si5323 2 Rev. 1.0