25 26 27 28 29 30 31 32 Si53311 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR WITH 2:1 INPUT MUX (<1.25 GHZ) Features 6 differential or 12 LVCMOS outputs Low output-output skew: <50 ps Ultra-low additive jitter: 100 fs rms Low propagation delay variation: <400 ps Wide frequency range: 1 MHz to 1.25 GHz Independent V and V : DD DDO Any-format input with pin selectable 1.8/2.5/3.3 V output formats: LVPECL, Low Power Excellent power supply noise LVPECL, LVDS, CML, HCSL, rejection (PSRR) LVCMOS Selectable LVCMOS drive strength to 2:1 mux with hot-swappable inputs tailor jitter and EMI performance Asynchronous output enable Small size: 32-QFN (5 mm x 5 mm) Output clock division: /1, /2, /4 RoHS compliant, Pb-free Ordering Information: Industrial temperature range: See page 25. 40 to +85 C Applications Pin Assignments High-speed clock distribution Storage Ethernet switch/router Telecom Si53311 Optical Transport Network (OTN) Industrial SONET/SDH Servers PCI Express Gen 1/2/3 Backplane clock distribution DIVA 24 DIVB 1 2 23 SFOUTB 1 SFOUTA 1 Description 3 22 SFOUTB 0 SFOUTA 0 21 Q5 4 Q0 GND PAD 5 20 Q0 Q5 The Si53311 is an ultra low jitter six output differential buffer with pin-selectable 6 19 V GND DDOB output clock signal format and divider selection. The Si53311 features a 2:1 mux, 7 18 V VDDOA DD CLK SEL 8 17 making it ideal for redundant clocking applications. The Si53311 utilizes Skyworks VREF Solutions advanced CMOS technology to fanout clocks from 1 MHz to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53311 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation Patents pending without the need for external circuitry. Functional Block Diagram Power Vref V REF Supply DIVA Generator Filtering V DDOA SFOUTA 1:0 OEA Q0, Q1, Q2 DivA Q0, Q1, Q2 CLK0 CLK0 DIVB VDDOB CLK1 SFOUTB 1:0 OEB CLK1 Q3, Q4, Q5 DivB Switching Q3, Q4, Q5 CLK SEL Logic Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.4 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021 9 Q1 NC CLK 10 Q1 0 CLK 11 Q2 0 Q2 OEA 12 13 Q3 OEB 14 Q3 CLK 1 15 Q4 CLK1 16 Q4 NCSi53311 TABLE OF CONTENTS Section Page 1. Electrical Specifications .3 2. Functional Description .10 2.1. Universal, Any-Format Input .10 2.2. Input Bias Resistors .12 2.3. Universal, Any-Format Output Buffer 12 2.4. Input Mux and Output Enable Logic .13 2.5. Flexible Output Divider .13 2.6. Input Mux and Output Enable Logic .14 2.7. Power Supply (V and V ) 14 DD DDOX 2.8. Output Clock Termination Options 15 2.9. AC Timing Waveforms .18 2.10. Typical Phase Noise Performance .19 2.11. Input Mux Noise Isolation 20 2.12. Power Supply Noise Rejection 21 3. Pin Description: 32-Pin QFN .22 4. Ordering Guide 25 5. Package Outline .26 5.1. 5x5 mm 32-QFN Package Diagram .26 6. PCB Land Pattern 27 6.1. 5x5 mm 32-QFN Package Land Pattern 27 7. Top Marking 28 7.1. Si53311 Top Marking 28 7.2. Top Marking Explanation .28 Contact Information 30 2 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com Rev. 0.4 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice September 3, 2021