Si53365-B-GTR Silicon Labs

Si53360/61/62/65 Data Sheet Low-Jitter, LVCMOS Fanout Clock Buffers with up to 12 outputs KEY FEATURES and Frequency Range from dc to 200 MHz Low additive jitter: 120 fs rms The Si53360/61/62/65 family of LVCMOS fanout buffers is ideal for clock/data distri- Built-in LDOs for high PSRR performance bution and redundant clocking applications. The family utilizes Skyworks advanced CMOS technology to fanout clocks from dc to 200 MHz with guaranteed low additive Up to 12 LVCMOS Outputs from LVCMOS inputs jitter, low skew, and low propagation delay variability. Built-in LDOs deliver high PSRR performance and eliminates the need for external components simplifying low jitter Frequency range: dc to 200 MHz clock distribution in noisy environments. Multiple configuration options Dual Bank option The CMOS buffers are available in multiple configurations with 8 outputs 2:1 Input MUX option (Si53360/61/65), or dual banks of 6 outputs each (Si53362). These buffers can be RoHS compliant, Pb-free paired with the Si534x clock generators and Si5xx oscillators to deliver end-to-end clock tree performance. Temperature range: 40 to +85 C VDD Power Supply VDDO (Si53361 only) Filtering OEA Si53360/61 8 8 Outputs VDD 0 CLK0 Power Supply Filtering VDDOA OEA 1 CLK1 OE 6 6 Outputs Si53365 8 Outputs Si53362 8 CLK SEL CLK 6 6 Outputs OEB VDDOB Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 1 Rev. 1.3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 3, 2021 1Table of Contents 1. Ordering Guide ..............................3 2. Functional Description............................4 2.1 LVCMOS Input Termination..........................4 2.2 Input Mux................................4 2.3 Output Clock Termination Options .......................5 2.4 AC Timing Waveforms ...........................6 2.5 Power Supply Noise Rejection.........................6 2.6 Typical Phase Noise Performance: Single-Ended Input Clock ..............7 2.7 Input Mux Noise Isolation ..........................8 3. Electrical Specifications ...........................9 4. Detailed Block Diagrams.......................... 12 5. Si5336x Pin Descriptions.......................... 15 5.1 Si53360 Pin Descriptions ..........................15 5.2 Si53361 Pin Descriptions ..........................17 5.3 Si53362 Pin Descriptions ..........................19 5.4 Si53365 Pin Descriptions ..........................21 6. Package Outline ............................. 22 6.1 16-Pin TSSOP Package...........................22 6.2 16-Pin QFN Package............................24 6.3 24-Pin QFN Package............................25 7. PCB Land Pattern ............................ 26 7.1 16-Pin TSSOP Land Pattern .........................26 7.2 16-Pin QFN Land Pattern ..........................27 7.3 24-Pin QFN Land Pattern ..........................29 8. Top Markings .............................. 31 8.1 Si53360/65 Top Markings ..........................31 8.2 Si53361 Top Marking............................32 8.3 Si53362 Top Marking............................33 9. Revision History............................. 34 Skyworks Solutions, Inc. Phone 781 376-3000 Fax 781 376-3100 sales skyworksinc.com www.skyworksinc.com 2 Rev. 1.3 Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice December 3, 2021 2