Si5341 Si5340 Si5341/40 Rev D Data Sheet Low-Jitter, 10 or 4-Output, Any-Frequency, Any-Output Clock KEY FEATURES Generator Generates any combination of output The any-frequency, any-output Si5341/40 clock generators combine a wide-band PLL frequencies from any input frequency with proprietary MultiSynth fractional synthesizer technology to offer a versatile and Ultra-low jitter of 90 fs rms high performance clock generator platform. This highly flexible architecture is capable Input frequency range: of synthesizing a wide range of integer and non-integer related frequencies up to 1 External crystal: 25 to 54 MHz GHz on 10 differential clock outputs while delivering sub-100 fs rms phase jitter per- Differential clock: 10 to 750 MHz formance with 0 ppm error. Each of the clock outputs can be assigned its own format and output voltage enabling the Si5341/40 to replace multiple clock ICs and oscillators LVCMOS clock: 10 to 250 MHz with a single device making it a trueclock tree on a chip Output frequency range: Differential: 100 Hz to 1028 MHz The Si5341/40 can be quickly and easily configured using ClockBuilderPro software. LVCMOS: 100 Hz to 250 MHz Custom part numbers are automatically assigned using a ClockBuilder Pro for fast, Highly configurable outputs compatible with 2 free, and easy factory pre-programming or the Si5341/40 can be programmed via I C LVDS, LVPECL, LVCMOS, CML, and HCSL and SPI serial interfaces. with programmable signal amplitude Si5341: 4 input, 10 output, 64-QFN 9x9 mm Si5340: 4 input, 4 output, 44-QFN 7x7 mm Applications: Clock tree generation replacing XOs, buffers, signal format translators Any-frequency clock translation Clocking for FPGAs, processors, memory Ethernet switches/routers OTN framers/mappers/processors Test equipment and instrumentation Broadcast video 25-54 MHz XTAL XA XB 4 Input OSC Clocks MultiSynth INT OUT0 IN0 INT MultiSynth INT OUT1 MultiSynth INT OUT2 INT IN1 PLL MultiSynth INT OUT3 IN2 INT MultiSynth INT OUT4 Up to 10 Output Clocks INT OUT5 Zero Delay INT OUT6 FB IN INT INT OUT7 Status Flags Status Monitor INT OUT8 INT OUT9 I2C / SPI Control NVM silabs.com Building a more connected world. Rev. 1.1 Si5341/40 Rev D Data Sheet Features List 1. Features List The Si5341/40 Rev D features are listed below: Generates any combination of output frequencies from any in- DCO mode: as low as 0.001 ppb steps put frequency Core voltage Ultra-low jitter of 90 fs rms VDD: 1.8 V 5% Input frequency range: VDDA: 3.3 V 5% External crystal: 25 to 54 MHz Independent output clock supply pins Differential clock: 10 to 750 MHz 3.3 V, 2.5 V, or 1.8 V LVCMOS clock: 10 to 250 MHz 2 Serial interface: I C or SPI Output frequency range: In-circuit programmable with non-volatile OTP memory Differential: 100 Hz to 1028 MHz ClockBuilder Pro software simplifies device configuration LVCMOS: 100 Hz to 250 MHz Si5341: 4 input, 10 output, 64-QFN 9x9 mm Highly configurable outputs compatible with LVDS, LVPECL, Si5340: 4 input, 4 output, 44-QFN 7x7 mm LVCMOS, CML, and HCSL with programmable signal ampli- Temperature range: 40 to +85 C tude Pb-free, RoHS-6 compliant Locks to gapped clock inputs Optional zero delay mode Glitchless on the fly output frequency changes silabs.com Building a more connected world. Rev. 1.1 2