Si5347/46 DUAL/QUAD DSPLL ANY-FREQUENCY, ANY-OUTPUT JITTER ATTENUATORS Features Four or two independent DSPLLs in Automatic free-run and holdover a single monolithic IC modes Each DSPLL generates any output Fastlock: <200 ms lock time frequency from any input frequency Glitchless on-the-fly DSPLL Input frequency range: frequency changes Differential: 8 kHz to 750 MHz DCO mode: as low as 0.01 ppb steps per DSPLL LVCMOS: 8 kHz to 250 MHz Core voltage: Output frequency range: Ordering Information: V : 1.8 V 5% Differential: up to 800 MHz DD See section 7 LVCMOS: up to 250 MHz V : 3.3 V 5% DDA Jitter performance: Independent output supply pins: <100 fs typ (12 kHz20 MHz) 3.3V, 2.5V, or 1.8V Flexible crosspoints route any input Pin Assignments Output-output skew: to any output clock <100 ps per DSPLL Programmable jitter attenuation Si5347 64QFN 2 Serial interface: I C or SPI Top View bandwidth per DSPLL: 0.1 Hz to In-circuit programmable with non- 4kHz volatile OTP memory Highly configurable outputs ClockBuilder Pro software tool IN1 1 48 FINC compatible with LVDS, LVPECL, IN1 2 47 LOL D simplifies device configuration 3 46 LVCMOS, programmable signal LOL A VDD 4 45 OUT4 LOL B Si5347: Quad DSPLL, 4 input, swings LOL C 5 44 OUT4 8 output, 64 QFN 6 43 RST VDDO4 Status monitoring (LOS, OOF, LOL) X1 7 42 FDEC Si5346: Dual DSPLL, 4 input, XA 8 GND 41 OE1 Hitless input clock switching: 9 40 XB Pad VDDS 4 output, 44 QFN automatic or manual X2 10 39 I2C SEL 38 OE0 11 OUT3 Temperature range: 40 to +85 C Locks to gapped clock inputs 12 37 OUT3 INTR Pb-free, RoHS-6 compliant VDDA 13 36 VDDO3 35 IN2 14 OUT2 IN2 15 34 OUT2 Applications SCLK 16 33 VDDO2 OTN Muxponders and Carrier Ethernet switches Transponders Broadcast video 10/40/100G network line cards Si5346 44QFN GbE/10GbE/100GbE Synchronous Top View Ethernet Description 1 33 The Si5347 is a high performance jitter attenuating clock multiplier which IN1 LOS XAXB 2 IN1 32 VDD integrates four any-frequency DSPLLs for applications that require maximum RST 3 31 OUT2 integration and independent timing paths. The Si5346 is a dual DSPLL version in 4 30 OUT2 X1 5 29 VDDO2 a smaller package. Each DSPLL has access to any of the four inputs and can XA GND th 6 28 LOL A XB provides low jitter clocks on any of the device outputs. Based on 4 generation Pad 7 27 LOL B X2 DSPLL technology, these devices provide any-frequency conversion with typical 26 VDDS VDDA 8 25 OUT1 VDDA 9 jitter performance of 100fs. Each DSPLL supports independent free-run, IN2 10 24 OUT1 holdover modes of operation, and offers automatic and hitless input clock 11 23 VDDO1 IN2 switching. The Si5347/46 is programmable via a serial interface with in-circuit programmable non-volatile memory so that it always powers up with a known configuration. Programming the Si5347/46 is made easy with Silicon Labs ClockBuilderPro software. Factory pre-programmed devices are also available. Preliminary Rev. 0.9 7/14 Copyright 2014 by Silicon Laboratories Si5347/46 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. 17 A1/SDO 64 IN0 12 44 OE0 IN0 SDA/SDIO 18 63 IN0 SDA/SDIO 13 43 IN0 A0/CS 19 62 IN3 14 42 RSVD 20 61 IN3 SCLK IN3 RSVD 21 60 VDD 15 A1/SDO 41 IN3 VDDO0 22 59 OUT7 A0/CS 16 40 VDD 23 OUT0 58 OUT7 INTR 17 39 VDD OUT0 24 57 VDDO7 18 38 LOS XAXB 25 56 RSVD VDDO0 I2C SEL 26 55 DSPLL SEL0 RSVD 19 37 OUT0 OE1 27 54 OUT6 DSPLL SEL1 20 36 OUT0 OUT3 NC 28 53 OUT6 21 35 VDD OUT3 29 52 VDDO1 VDDO6 34 NC 22 VDDO3 OUT1 30 51 OUT5 OUT1 31 50 OUT5 VDD 32 49 VDDO5Si5347 Si5346 Si5347/46 Functional Block Diagram XTAL/ REFCLK XA XB Si5347/46 OSC INT OUT0 INT OUT1 DSPLL IN0 FRAC A INT OUT2 DSPLL IN1 FRAC B INT OUT3 INT DSPLL OUT4 IN2 FRAC C INT OUT5 DSPLL IN3 FRAC D INT OUT6 NVM INT OUT7 2 I C/SPI Control/ Status 2 Preliminary Rev. 0.9