SL2309 Not Recommended for New Designs Low Jitter and Skew 10 to 140 MHz Zero Delay Buffer (ZDB) Key Features Description 10 to 140 MHz operating frequency range The SL2309 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) Low output clock jitter: clock outputs from one (1) reference input clock, for high 140 ps-max cycle-to-cycle jitter speed clock distribution applications. Low output-to-output skew: 150 ps-max The product has an on-chip PLL which locks to the input Low product-to-product skew: 400 ps-max clock at CLKIN and receives its feedback internally from 3.3 V power supply range the CLKOUT pin. Low power dissipation: The SL2309 has two (2) clock driver banks each with four 26 mA-max at 66 MHz (4) clock outputs. These outputs are controlled by two (2) 44 mA max at 133 MHz select input pins S1 and S2. When only four (4) outputs One input drives 9 outputs organized as 4+4+1 are needed, four (4) bank-B output clock buffers can be tri- stated to reduce power dissipation and jitter. The select Select mode to bypass PLL or tri-state outputs inputs can also be used to tri-state both banks A and B or SpreadThru PLL that allows use of SSCG drive them directly from the input bypassing the PLL and Standard and High-Drive options making the product behave like a Non-Zero Delay Fanout Available in 16-pin SOIC and TSSOP packages Buffer (NZDB). Available in Commercial and Industrial grades The high-drive (-1H) version operates up to 140MHz and low drive (-1) version operates up to 100MHz at 3.3V. Applications Printers and MFPs Benefits Digital Copiers Up to nine (9) distribution of input clock PCs and Work Stations Standard and High-Drive levels to control impedance DTV level, frequency range and EMI Routers, Switchers and Servers Low power dissipation, jitter and skew Digital Embeded Systems Low cost Block Diagram Low Power and Low Jitter PLL MUX CLKOUT CLKIN CLKA1 CLKA2 CLKA3 CLKA4 S2 Input Selection Decoding Logic S1 CLKB1 CLKB2 CLKB3 2 2 CLKB4 VDD GND Rev 2.0, May 12, 2008 Page 1 of 12 400 West Cesar Chavez, Austin, TX 78701 1 (512) 416-8500 1 (512) 416-9669 www.silabs.com Not Recommended for New Designs SL2309 Pin Configuration 16 CLKOUT CLKIN 1 CLKA1 15 2 CLKA4 CLKA2 14 CLKA3 3 VDD VDD 13 4 GND 5 12 GND CLKB1 11 CLKB4 6 CLKB3 CLKB2 10 7 S1 S2 9 8 16-Pin SOIC and TSSOP Pin Description Pin Pin Name Pin Type Pin Description Number 1 CLKIN Input Reference Frequency Clock Input. Weak pull-down (250k). 2 CLKA1 Output Buffered Clock Output, Bank A. Weak pull-down (250k). 3 CLKA2 Output Buffered Clock Output, Bank A. Weak pull-down (250k). 4 VDD Power 3.3V Power Supply. 5 GND Power Power Ground. 6 CLKB1 Output Buffered Clock Output, Bank B. Weak pull-down (250k). 7 CLKB2 Output Buffered Clock Output, Bank B. Weak pull-down (250k). 8 S2 Input Select Input, select pin S2. Weak pull-up (250k). 9 S1 Input Select Input, select pin S1. Weak pull-up (250k). 10 CLKB3 Output Buffered Clock Output, Bank B. Weak pull-down (250k). 11 CLKB4 Output Buffered Clock Output, Bank B. Weak pull-down (250k). 12 GND Power Power Ground. 13 VDD Power 3.3V Power Supply. 14 CLKA3 Output Buffered Clock Output, Bank A. Weak pull-down (250k). 15 CLKA4 Output Buffered Clock Output, Bank A. Weak pull-down (250k). 16 CLKOUT Output Buffered Clock Output, PLL Internal Feedback Output. Weak pull-down (250k). Rev 2.0, May 12, 2008 Page 2 of 12 Not Recommended for New Designs