SL2304NZ Not Recommended for New Designs Low Jitter and Skew DC to 140MHz Clock Buffer Key Features Description The SL2304NZ is a low skew, jitter and power fanout DC to 140 MHz operating frequency range Buffer designed to produce up to four (4) clock outputs Low output clock skew: 50ps-typ from one (1) reference input clock, for high speed clock Low part-to-part output skew: 100 ps-typ distribution, including PCI/PCI-X applications. Low output propogation delay: 2.5ns-typ The SL2304NZ products operate from DC to 140MHz. 3.3V +/-10% operation supply voltage The only difference between SL2304NZ-1 and SL2304NZ- Low power dissipation: 1Z is the OE logic implementation. Refer to the Available - 7 mA-typ at 33MHz OE Logic Configuration Table. 1 - 9 mA-typ at 66MHz Refer to SL23EP04NZ products for DC to 220MHz-max - 12 mA-typ at 133MHz frequency range and 2.5V to 3.3V power supply operation, One input to four output fanout buffer drivers improved skew, jitter and higher drive options. Output Enable (OE) control function Benefits Available in 8-pin TSSOP package Up to four (4) distribution of input clock Available in Commercial and Industrial grades Low propogation delay Available in Lead (Pb) free package Low output-to-output skew Applications Low output clock Jitter Low power dissipation General Purpose PCI/PCI-X Clock Buffer Printers, MFPs and Digital Copiers PCs and Work Stations Routers, Switches and Servers Datacom and Telecom High-Speed Digital Embeded Systems Block Diagram Logic OE Control CLK1 CLK2 CLKIN CLK3 CLK4 VDD GND Rev 2.1, May 6, 2008 Page 1 of 9 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com Not Recommended for New DesignsSL2304NZ Pin Configuration CLKIN 1 8 CLK4 OE 2 CLK3 7 CLK1 3 6 VDD 4 5 CLK2 GND 8-Pin TSSOP Pin Description Pin Pin Name Pin Type Pin Description Number 1 CLKIN Input Reference Clock Input 2 OE Output Output Enable. Refer to the Table. 1 for Logic Table 3 CLK1 Output Buffered Clock Output 1 4 GND Power Power Ground. 5 CLK2 Output Buffered Clock Output 2 6 VDD Output 3.3V Power Supply 7 CLK3 Power Buffered Clock Output 3 8 CLK4 Input Buffered Clock Output 4 Rev 2.1, May 6, 2008 Page 2 of 9 Not Recommended for New Designs