SL23EP08 Not Recommended for New Designs Low Jitter and Skew 10 to 220 MHz Zero Delay Buffer (ZDB) Key Features Description 10 to 220 MHz operating frequency range The SL23EP08 is a low skew, low jitter and low power Zero Delay Buffer (ZDB) designed to produce up to nine (9) clock Low output clock skew: 45ps-typ outputs from one (1) reference input clock, for high speed clock Low output clock jitter: distribution applications. 25 ps-typ cycle-to-cycle jitter The product has an onc-hip PLL and a feedback pin (FBK) 15 ps-typ period jitter which can be used to obtain feedback from any one of the Low part-to-part output skew: 90 ps-typ output clocks. The SL23EP08 has two (2) clock driver banks Wide 2.5 V to 3.3 V power supply range each with four (4) clock outputs. These outputs are controlled Low power dissipation: by two (2) select input pins S1 and S2. When only four (4) outputs are needed, four (4) bank -B output clock buffers can be 20 mA-max at 66 MHz and VDD=3.3 V tri-stated to reduce power dissipation and jitter. The select 18 mA-max at 66 MHz and VDD=2.5V inputs can also be used to tri-state both banks A and B or drive One input drives 8 outputs them directly from the input bypassing the PLL and making the Multiple configurations and drive options product behave like a NonZer- o Delay Buffer (NZDB). The product also offers various 1X, 2X and 4X frequency options at Select mode to bypass PLL or tri-state outputs the output clocks. Refer to the Product Configuration Table SpreadThru PLL that allows use of SSCG for the details. Available in 16-pin SOIC and TSSOP packages The high-drive version operates up to 220MHz and 200MHz at Available in Commercial and Industrial grades 3.3V and 2.5V power supplies respectively. Applications Benefits Printers, MFPs and Digital Copiers Up to eight (8) distribution of input clock PCs and Work Stations Standard and High-Dirive levels to control impedance Routers, Switchers and Servers level, frequency range and EMI Datacom and Telecom Low power dissipation, jitter and skew High-SpeedDigital Embeded Systems Low cost Block Diagram /2 Low Power and (Divider for -3 and -4 only) Low Jitter PLL CLKIN /2 MUX FBK (Divider for -5H only) CLKA1 CLKA2 CLKA3 CLKA4 S2 Input Selection Decoding Logic S1 /2 (Divider for -2 and -3 only) CLKB1 CLKB2 CLKB3 2 2 CLKB4 VDD GND Rev 1.1, Feb 11, 2016 Page 1 of 17 2400 West Cesar Chavez, Austin, TX 78701 1+(512) 416-8500 1+(512) 416-9669 www.silabs.com Not Recommended for New Designs SL23EP08 16-Pin SOIC and TSSOP Pin Configuration 16 CLKIN 1 FBK CLKA1 15 2 CLKA4 CLKA2 14 CLKA3 3 VDD VDD 13 4 12 GND 5 GND CLKB1 11 CLKB4 6 CLKB3 CLKB2 10 7 S1 S2 9 8 Pin Description Pin Pin Name Pin Type Pin Description Number 1 Input CLKIN Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (250k). 2 Output CLKA1 Buffered Clock Output, Bank A. Weak pull-down (250k). 3 Output CLKA2 Buffered Clock Output, Bank A. Weak pull-down (250k). 4 Power VDD 3.3V or 2.5V Power Supply. 5 Power GND Power Ground. 6 Output CLKB1 Buffered Clock Output, Bank B. Weak pull-down (250k). 7 Output CLKB2 Buffered Clock Output, Bank B. Weak pull-down (250k). 8 Input S2 Select Input, select pin S2. Weak pull-up (250k). 9 Input S1 Select Input, select pin S1. Weak pull-up (250k). 10 Output CLKB3 Buffered Clock Output, Bank B. Weak pull-down (250k). 11 Output CLKB4 Buffered Clock Output, Bank B. Weak pull-down (250k). 12 Power GND Power Ground. 13 Power VDD 3.3V or 2.5V Power Supply. 14 Output CLKA3 Buffered Clock Output, Bank A. Weak pull-down (250k). 15 Output CLKA4 Buffered Clock Output, Bank A. Weak pull-down (250k). 16 Output FBK PLL Feedback input. Rev 1.1, Feb 11, 2016 P age 2 of 17 Not Recommended for New Designs