74AC374TTR STMicroelectronics

74AC374 OCTAL D-TYPE FLIP-FLOP WITH 3 STATE OUTPUTS (NON INVERTED) HIGH SPEED: f = 270MHz (TYP.) at V = 5V MAX CC LOW POWER DISSIPATION: I = 4A(MAX.) at T =25C CC A HIGH NOISE IMMUNITY: V = V = 28 % V (MIN.) NIH NIL CC DIP SOP TSSOP 50 TRANSMISSION LINE DRIVING CAPABILITY SYMMETRICAL OUTPUT IMPEDANCE: ORDER CODES I = I = 24mA (MIN) OH OL BALANCED PROPAGATION DELAYS: PACKAGE TUBE T & R t t PLH PHL DIP 74AC374B OPERATING VOLTAGE RANGE: SOP 74AC374M 74AC374MTR V (OPR) = 2V to 6V CC TSSOP 74AC374TTR PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 374 the D inputs. IMPROVED LATCH-UP IMMUNITY While the (OE) input is low, the 8 outputs will be in a normal logic state (high or low logic level) while DESCRIPTION OE is in high level, the outputs will be in a high impedance state. The 74AC374 is an advanced high-speed CMOS OCTAL D-TYPE FLIP-FLOP with 3 STATE The output control does not affect the internal operation of flip-flops that is, the old data can be OUTPUT NON INVERTING fabricated with retained or the new data can be entered even sub-micron silicon gate and double-layer metal 2 while the outputs are off. wiring C MOS technology. All inputs and outputs are equipped with These 8 bit D-Type Flip-Flop are controlled by a protection circuits against static discharge, giving clock input (CK) and an output enable input (OE). them 2KV ESD immunity and transient excess On the positive transition of the clock, the Q voltage. outputs will be set to the logic that were setup at PIN CONNECTION AND IEC LOGIC SYMBOLS April 2001 1/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) 74AC374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No SYMBOL NAME AND FUNCTION 1OE 3-State Output Enable (Active LOW) 2, 5, 6, 9, 12, Q0 to Q7 3-State Outputs 15, 16,19 3, 4, 7, 8, 13, D0 to D7 Data Inputs 14, 17, 18 11 CLOCK Clock Input (LOW-to-HIGH Edge Trigger) 10 GND Ground (0V) 20 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUT OE CK D Q H XXZ L X NO CHANGE LLL H LH X : Dont Care Z : High Impedance LOGIC DIAGRAM This logic diagram has not be used to estimate propagation delays 2/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)