74ALVCH16374 LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS 3.6V TOLERANT INPUTS AND OUTPUTS HIGH SPEED : t = 4.2 ns (MAX.) at V =3.0 to3.6V PD CC t = 5.3 ns (MAX.) at V =2.3 to2.7V PD CC t = 6.5 ns (MAX.) at V =1.65V PD CC POWER DOWN PROTECTION ON INPUTS AND OUTPUTS TSSOP SYMMETRICAL OUTPUT IMPEDANCE: I = I = 24mA (MIN) at V =3.0V OH OL CC I = I = 18mA (MIN) at V =2.3V OH OL CC ORDER CODES I = I =4mA (MIN)atV = 1.65V OH OL CC PACKAGE TUBE T & R OPERATING VOLTAGE RANGE: TSSOP 74ALVCH16374TTR V (OPR) = 1.65V to 3.6V CC PIN AND FUNCTION COMPATIBLE WITH PIN CONNECTION 74 SERIES 16374 BUS HOLD PROVIDED ON DATA INPUTS LATCH-UP PERFORMANCE EXCEEDS 300mA (JESD 17) ESD PERFORMANCE: HBM > 2000V (MIL STD 883 method 3015) MM > 200V DESCRIPTION The 74ALVCH16374 is a low voltage CMOS 16 BIT D-TYPE FLIP-FLOP with 3 STATE OUTPUTS NON INVERTING fabricated with sub-micron 2 silicon gate and five-layer metal wiring C MOS technology. It is ideal for low power and very high speed 1.65 to 3.6V applications it can be interfaced to 3.6V signal environment for both inputs and outputs. These 16 bit D-TYPE flip-flops are controlled by two clock inputs (nCK) and two output enable inputs (nOE). On thepositivetransitionof the (nCK), thenQ outputs will be set to the logic state that were setup at the nD inputs. While the (nOE) input is low, the outputs (nQ) will be in a normal state (HIGH or LOW logic level) and while high level the outputs will be in a high impedance state. Any output control does not affect the internal operation of flip flops that is, the old data can be retained or the new data can be entered even while the outputs are off. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. February 2003 1/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) 74ALVCH16374 INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION IEC LOGIC SYMBOLS PIN No SYMBOL NAME AND FUNCTION 1 1OE 3 State Output Enable Input (Active LOW) 2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs 11, 12 13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs 19, 20, 22, 23 24 2OE 3 State Output Enable Input (Active LOW) 25 2CK Clock Input 36, 35, 33, 32, 2D0 to 2D7 Data Inputs 30, 29, 27, 26 47, 46, 44, 43, 1D0 to 1D7 Data Inputs 41, 40, 38, 37 48 1CK Clock Input 4, 10, 15, 21, GND Ground (0V) 28, 34, 39, 45 7, 18, 31, 42 V Positive Supply Voltage CC TRUTH TABLE INPUTS OUTPUT OE CK D Q HX X Z L X NO CHANGE LL L LH H X : Dont Care Z : High Impedance 2/11 Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)