74ALVT162821DGGS NXP

74ALVT162821 20-bit bus interface D-type flip-flop positive-edge trigger with 30 termination resistors 3-state Rev. 5 19 October 2020 Product data sheet 1. General description The 74ALVT162821 is a 20-bit positive-edge triggered D-type flip-flop with 30 termination resistors and 3-state outputs The device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 10-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs 2. Features and benefits Wide supply voltage range from 2.3 V to 3.6 V Overvoltage tolerant inputs to 5.5 V BiCMOS high speed and output drive Outputs include series resistance of 30 making external termination resistors unnecessary No bus current loading when output is tied to 5 V bus Direct interface with TTL levels I circuitry provides partial Power-down mode operation OFF 20-bit positive-edge triggered register 5 V I/O compatible Multiple V and GND pins minimize switching noise CC Bus hold on data inputs Live insertion and extraction permitted Power-up reset Power-up 3-state Output capability: +12 mA and -12 mA Latch-up protection: JESD17: exceeds 500 mA ESD protection: MIL STD 883, method 3015: exceeds 2000 V MM: exceeds 200 V Specified from -40 C to 85 C 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVT162821DGG -40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mmNexperia 74ALVT162821 20-bit bus interface D-type flip-flop positive-edge trigger with 30 termination resistors 3-state 4. Functional diagram 1 1OE EN2 56 1CP C1 28 2OE EN4 29 2CP C3 2 55 1D0 1D 2 1Q0 54 3 1D1 1Q1 55 54 52 51 49 48 47 45 44 43 5 52 1D2 1Q2 51 6 1D3 1Q3 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 49 8 1D4 1Q4 56 1CP 48 9 1D5 1Q5 47 10 1 1OE 1D6 1Q6 45 12 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 1D7 1Q7 44 13 1D8 1Q8 43 14 2 3 5 6 8 9 10 12 13 14 1D9 1Q9 15 42 2D0 3D 4 2Q0 41 16 2D1 2Q1 42 41 40 38 37 36 34 33 31 30 40 17 2D2 2Q2 38 19 2D3 2Q3 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 37 20 2D4 2Q4 29 2CP 21 36 2D5 2Q5 34 23 28 2OE 2D6 2Q6 24 33 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2D7 2Q7 31 26 2D8 2Q8 30 27 15 16 17 19 20 21 23 24 26 27 2D9 2Q9 001aad153 001aad155 Fig. 1. Logic symbol Fig. 2. IEC logic symbol nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 001aad156 Fig. 3. Logic diagram V V CC CC 27 output 27 001aac372 Fig. 4. Schematic of each output 74ALVT162821 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2020. All rights reserved Product data sheet Rev. 5 19 October 2020 2 / 15