74ALVT16543DL,518 NXP

INTEGRATED CIRCUITS 74ALVT16543 2.5 V/3.3 V ALVT 16-bit registered transceiver (3-State) Product data sheet 2004 Sep 14 Supersedes data of 1998 Feb 13 
   Philips Semiconductors Product data sheet 2.5 V/3.3 V 16-bit registered transceiver (3-State) 74ALVT16543 FEATURES DESCRIPTION 16-bit universal bus interface The 74ALVT16543 is a high-performance BiCMOS product designed for V operation at 2.5 V or 3.3 V with I/O compatibility 5 V I/O Compatible CC up to 5 V. The device can be used as two 8-bit transceivers or one 3-State buffers 16-bit transceiver. Output capability: +64 mA/32 mA The 74ALVT16543 contains two sets of eight D-type latches, with TTL input and output switching levels separate control pins for each set. Using data flow from A to B as an Input and output interface capability to systems at 5 V supply example, when the A-to-B Enable (nEAB) input and the A-to-B Latch Bus-hold data inputs eliminate the need for external pull-up Enable (nLEAB) input are LOW, the A-to-B path is transparent. resistors to hold unused inputs A subsequent LOW-to-HIGH transition of the nLEAB signal puts the Live insertion/extraction permitted A data into the latches where it is stored and the B outputs no longer Power-up 3-State change with the A inputs. With nEAB and nOEAB both LOW, the Power-up reset 3-State B output buffers are active and display the data present at No bus current loading when output is tied to 5 V bus the outputs of the A latches. Latch-up protection exceeds 500mA per JEDEC Std 17 Control of data flow from B to A is similar, but using the nEBA, ESD protection exceeds 2000 V per MIL STD 883 Method 3015 nLEBA, and nOEBA inputs. and 200 V per Machine Model Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA TYPICAL CONDITIONS SYMBOLSYMBOL PPARAMETERARAMETER UNITUNIT T = 25 C; GND = 0 V amb 2.5 V 3.3 V t Propagation delay 1.8 1.6 PLH C = 50 pF ns L t nAx to nBx or nBx to nAx 2.7 1.8 PHL C Input capacitance DIR, OE V = 0 V or V 3 3 pF IN I CC C I/O pin capacitance Outputs disabled; V = 0 V or V 9 9 pF I/O I/O CC I Total supply current Outputs disabled 40 70 A CCZ ORDERING INFORMATION PACKAGES TEMPERATURE RANGE TYPE NUMBER DWG NUMBER 56-Pin Plastic SSOP Type III 40 C to +85 C 74ALVT16543DL SOT371-1 56-Pin Plastic TSSOP Type II 40 C to +85 C 74ALVT16543DGG SOT364-1 LOGIC SYMBOL (IEEE/IEC) 56 29 1EN3 (BA) 7EN9 (BA) 54 31 G1 G7 55 30 1C5 7C11 1 28 2EN4 (AB) 8EN10 (AB) 3 26 G2 G8 2 27 2C6 8C12 5 52 15 42 3 5 D 9 11 D 4 6 D 12 D 10 6 51 16 41 8 49 17 40 9 48 19 38 10 47 20 37 12 45 21 36 13 44 23 34 14 43 24 33 SW00151 2004 Sep 14 2