74ALVT16821DL NXP

74ALVT16821 20-bit bus interface D-type ip-op positive-edge trigger 3-state Rev. 03 13 June 2005 Product data sheet 1. General description The 74ALVT16821 high-performance Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for V operation at 2.5 V or 3.3 V with CC I/O compatibility to 5 V. The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding ip-ops Q output. The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active low output enable (nOE) controls all ten 3-state buffers independent of the register operation. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will neither drive nor load the bus. 2. Features 20-bit positive-edge triggered register 5 V I/O compatible Multiple V and GND pins minimize switching noise CC Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up reset Power-up 3-state Output capability: +64 mA and - 32 mA Latch-up protection: JESD78: exceeds 500 mA ESD protection: MIL STD 883, method 3015: exceeds 2000 V Machine model: exceeds 200 V74ALVT16821 Philips Semiconductors 20-bit bus interface D-type ip-op positive-edge trigger 3-state 3. Quick reference data Table 1: Quick reference data GND = 0 V T = 25 C. amb Symbol Parameter Conditions Min Typ Max Unit V = 2.5 V CC t propagation delay nCP to nQx C = 50 pF - 2.6 - ns PLH L t propagation delay nCP to nQx C = 50 pF - 2.7 - ns PHL L C input capacitance V = 0 V or V 3- pF i I CC C output capacitance V = 0 V or V 9- pF o O CC I supply current outputs disabled - 40 - A CC V = 3.3 V CC t propagation delay nCP to nQx C = 50 pF - 1.7 - ns PLH L t propagation delay nCP to nQx C = 50 pF - 1.8 - ns PHL L C input capacitance V = 0 V or V 3- pF i I CC C output capacitance V = 0 V or V 9- pF o O CC I supply current outputs disabled - 70 - A CC 4. Ordering information Table 2: Ordering information Type number Package Temperature range Name Description Version 74ALVT16821DL - 40 C to +85 C SSOP56 plastic shrink small outline package 56 leads SOT371-1 body width 7.5 mm 74ALVT16821DGG - 40 C to +85 C TSSOP56 plastic thin shrink small outline package SOT364-1 56 leads body width 6.1 mm 9397 750 15123 Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 13 June 2005 2 of 18