74ALVT162823DGGS NXP

74ALVT162823 18-bit bus-interface D-type flip-flop with reset and enable with 30 termination resistors 3-state Rev. 3 23 January 2018 Product data sheet 1 General description The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data or address paths of buses carrying parity. The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed systems. The registers are fully edge-triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the flip-flop. The 74ALVT162823 is designed with 30 series resistance in both the pull-up and pull-down output structures. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus receivers or transmitters. 2 Features and benefits Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops 5 V I/O compatible Ideal where high speed, light loading or increased fan-in are required with MOS microprocessors Bus hold data inputs eliminate the need for external pull-up resistors to hold unused inputs Live insertion and extraction permitted Power-up 3-state Power-up reset Output capability: +12 mA to 12 mA Outputs include series resistance of 30 making external termination resistors unnecessary Latch-up protection: JESD78: exceeds 500 mA ESD protection: MIL STD 883, method 3015: exceeds 2000 V MM: exceeds 200 VNexperia 74ALVT162823 18-bit bus-interface D-type flip-flop with reset and enable with 30 termination resistors 3-state 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVT162823DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mm 4 Functional diagram 2 V CC 1OE EN1 1 1MR R2 55 1CE G3 56 1CP 3C4 27 2OE EN5 28 2MR R6 30 data input to internal circuit 2CE G7 29 2CP 7C8 54 3 1D0 4D 1,2 1Q0 52 5 1D1 1Q1 51 6 1D2 1Q2 001aad245 49 8 1D3 1Q3 Figure 2.Bus hold circuit 48 9 1D4 1Q4 47 10 1D5 1Q5 45 12 V CC 1D6 1Q6 44 13 1D7 1Q7 V CC 43 14 1D8 1Q8 42 15 8D 5,6 2D0 2Q0 41 16 2D1 2Q1 40 17 2D2 2Q2 27 38 19 2D3 2Q3 37 20 output 2D4 2Q4 36 21 2D5 2Q5 27 34 23 2D6 2Q6 33 24 2D7 2Q7 31 26 2D8 2Q8 001aad242 001aad244 Figure 1.IEC logic symbol Figure 3.Schematic of each output 74ALVT162823 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 23 January 2018 2 / 18