74ALVCH16821DGGS Nexperia

74ALVCH16821 20-bit bus-interface D-type flip-flop positive-edge trigger 3-state Rev. 3 2 February 2018 Product data sheet 1 General description The 74ALVCH16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates. Each register is fully edge triggered. The state of each nDn input, one set-up time before the Low-to-High clock transition, is transferred to the corresponding flip-flops nQn output. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16821 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits Wide supply voltage range from 1.2 V to 3.6 V CMOS low-power consumption Direct interface with TTL levels Current drive 24 mA at 3.0 V MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Output drive capability 50 transmission lines at 85C All data inputs have bushold Complies with JEDEC standard no. 8-1A Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH16821DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mmNexperia 74ALVCH16821 20-bit bus-interface D-type flip-flop positive-edge trigger 3-state 4 Functional diagram 1 1OE EN2 56 C1 1CP 28 EN4 2OE 29 2CP C3 55 2 1D 2 1D0 1Q0 54 3 1D1 1Q1 55 54 52 51 49 48 47 45 44 43 52 5 1D2 1Q2 51 6 1D3 1Q3 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 49 8 1D4 1Q4 56 1CP 48 9 1D5 1Q5 47 10 1 1OE 1D6 1Q6 45 12 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 1D7 1Q7 44 13 1D8 1Q8 14 43 2 3 5 6 8 9 10 12 13 14 1D9 1Q9 42 15 2D0 2Q0 3D 4 16 41 2D1 2Q1 42 41 40 38 37 36 34 33 31 30 40 17 2D2 2Q2 38 19 2D3 2Q3 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 37 20 2D4 2Q4 29 2CP 36 21 2D5 2Q5 34 23 28 2OE 2D6 2Q6 33 24 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 2D7 2Q7 31 26 2D8 2Q8 30 27 15 16 17 19 20 21 23 24 26 27 2D9 2Q9 001aad153 001aad155 Figure 1.Logic symbol Figure 2.IEC logic symbol nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 001aad156 Figure 3.Logic diagram 74ALVCH16821 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved. Product data sheet Rev. 3 2 February 2018 2 / 15