74ALVCH16841DGGS Nexperia

74ALVCH16841 20-bit bus interface D-type latch 3-state Rev. 3 12 September 2018 Product data sheet 1. General description The 74ALVCH16841 has two 10-bit D-type latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appears at the outputs. When nOE is HIGH the outputs are in High-impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16841 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2. Features and benefits Wide supply voltage range of 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Current drive 24 mA at V = 3.0 V CC MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimize noise and ground bounce CC All data inputs have bushold Output drive capability 50 transmission lines at 85 C 3-state non-inverting outputs for bus oriented applications Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVCH16841DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package 56 leads SOT364-1 body width 6.1 mmNexperia 74ALVCH16841 20-bit bus interface D-type latch 3-state 4. Functional diagram 1 1OE EN2 1OE 2OE 56 1LE C1 28 1 28 2OE EN4 29 55 2 2LE C3 1D0 1Q0 54 3 1D1 1Q1 55 2 52 5 1D0 1D 2 1Q0 1D2 1Q2 54 3 51 6 1D1 1Q1 1D3 1Q3 52 5 49 8 1D2 1Q2 1D4 1Q4 51 6 48 9 1D3 1Q3 1D5 1Q5 49 8 47 10 1D4 1Q4 1D6 1Q6 48 9 45 12 1D5 1Q5 1D7 1Q7 47 10 44 13 1D6 1Q6 1D8 1Q8 45 12 43 14 1D7 1Q7 1D9 1Q9 44 13 42 15 1D8 1Q8 2D0 2Q0 43 14 41 16 1D9 1Q9 2D1 2Q1 42 15 40 17 2D0 3D 4 2Q0 2D2 2Q2 41 16 38 19 2D1 2Q1 2D3 2Q3 40 17 37 20 2D2 2Q2 2D4 2Q4 38 19 36 21 2D3 2Q3 2D5 2Q5 37 20 34 23 2D4 2Q4 2D6 2Q6 36 21 33 24 2D5 2Q5 2D7 2Q7 34 23 31 26 2D6 2Q6 2D8 2Q8 33 24 30 27 2D7 2Q7 2D9 2Q9 31 26 2D8 2Q8 56 29 30 27 2D9 2Q9 1LE 2LE aaa-029040 aaa-029041 Fig. 1. Logic symbol Fig. 2. IEC logic symbol 1D0 D Q 1Q0 2D0 D Q 2Q0 LATCH LATCH 1 11 LE LE 1LE 2LE 1OE 2OE to 9 other channels to 9 other channels aaa-029042 Fig. 3. Logic diagram V CC data to internal circuit input mna004 Fig. 4. Bushold circuit 74ALVCH16841 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 3 12 September 2018 2 / 12