74ALVCH16843DGGS NXP

74ALVCH16843 18-bit bus-interface D-type latch 3-State Rev. 3 20 November 2017 Product data sheet 1 General description The 74ALVCH16843 has two 9bit D-type latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. The two sections of each register are controlled independently by the latch enable (nLE), clear (nCLR), preset (nPRE) and output enable (nOE) control gates. When nOE is LOW, the data in the registers appear at the outputs. When nOE is HIGH, the outputs are in the high impedance OFF state. Operation of the nOE input does not affect the state of the flip-flops. The 74ALVCH16843 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors. 2 Features and benefits Wide supply voltage range of 1.2V to 3.6V CMOS low power consumption Direct interface with TTL levels Current drive 24 mA at V = 3.0 V. CC MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimize noise and ground bounce CC All data inputs have bushold Output drive capability 50 transmission lines at 85 C 3-state non-inverting outputs for bus oriented applications Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3 Ordering information Table 1.Ordering information Type number Package Temperature range Name Description Version 74ALVCH16843DGG -40 C to +85 C TSSOP56 plastic thin shrink small outline package SOT364-1 56 leads body width 6.1 mmNexperia 74ALVCH16843 18-bit bus-interface D-type latch 3-State 4 Functional diagram 2 1 55 2 56 1OE EN4 55 1PRE S2 1 1CLR R3 1CLR 1PRE 1OE 1LE 56 1LE C1 3 1Q0 1D0 54 27 2OE EN8 30 5 1Q1 1D1 52 2PRE S6 28 6 1Q2 1D2 51 2CLR R7 29 2LE C5 8 1Q3 1D3 49 9 1Q4 1D4 48 54 3 1D0 1D 2, 3, 4 1Q0 10 1Q5 1D5 47 52 5 1D1 1Q1 12 1Q6 1D6 45 51 6 1D2 1Q2 13 1Q7 1D7 44 49 8 1D3 1Q3 48 9 14 1Q8 1D8 43 1D4 1Q4 47 10 15 2Q0 2D0 42 1D5 1Q5 45 12 16 2Q1 2D1 41 1D6 1Q6 44 13 1D7 1Q7 17 2Q2 2D2 40 43 14 1D8 1Q8 19 2Q3 2D3 38 42 15 2D0 5D 6, 7, 8 2Q0 20 2Q4 2D4 37 41 16 2D1 2Q1 40 17 21 2Q5 2D5 36 2D2 2Q2 38 19 23 2Q6 2D6 34 2D3 2Q3 37 20 24 2Q7 2D7 33 2D4 2Q4 36 21 2D5 2Q5 26 2Q8 2D8 31 34 23 2D6 2Q6 2CLR 2PRE 2OE 2LE 33 24 2D7 2Q7 31 26 2D8 2Q8 28 30 27 29 aaa-027720 aaa-027721 Figure 1.Logic symbol Figure 2.IEC logic symbol LATCH 1 LATCH 10 1D0 D Q 1Q0 2D0 D Q 2Q0 1CLR CLR 2CLR CLR PRE PRE 1PRE LE 2PRE LE 1LE 2LE 1OE 2OE to 8 other channels to 8 other channels aaa-027722 Figure 3.Logic diagram 74ALVCH16843 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2017. All rights reserved. Product data sheet Rev. 3 20 November 2017 2 / 16