IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE IDT74ALVCH162373 3.3V CMOS 16-BIT TRANS- PARENT D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology This 16-bit transparent D-type latch is built using advanced dual metal CMOS Typical tSK(o) (Output Skew) < 250ps technology. The ALVCH162373 is particularly suitable for imple-menting buffer ESD > 2000V per MIL-STD-883, Method 3015 > 200V using registers, I/O ports, bidirectional bus drivers, and working registers. This device machine model (C = 200pF, R = 0) can be used as two 8-bit latches or one16-bit latch. When the latch enable (LE) VCC = 3.3V 0.3V, Normal Range input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the VCC = 2.7V to 3.6V, Extended Range Q outputs are latched at the levels set up at the D inputs. VCC = 2.5V 0.2V A buffered output-enable (OE) can be used to place the eight outputs in either CMOS power levels (0.4 W typ. static) a normal logic state (high or low logic levels) or a high-impedance state. In the Rail-to-Rail output swing for increased noise margin high-impedance state, the outputs neither load nor drive the bus lines signifi- Available in SSOP and TSSOP packages cantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components. OE does not DRIVE FEATURES: affect internal operations of the latch. Old data can be retained or new data can Balanced Output Drivers: 12mA be enetered while the outputs are in the high-impedance state. Low switching noise The ALVCH162373 has series resistors in the device output structure which will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. APPLICATIONS: The ALVCH162373 has bus-hold which retains the inputs last state 3.3V high speed systems whenever the input goes to a high impedance. This prevents floating inputs and 3.3V and lower voltage computing systems eliminates the need for pull-up/down resistor. FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 48 25 2LE 1LE C1 C1 2 13 1Q1 2Q1 47 36 1D1 1D 1D 2D1 TO 7 OTHER CHANNELS TO 7 OTHER CHANNELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JUNE 2016 1 2016 Integrated Device Technology, Inc. DSC-4575/7IDT74ALVCH162373 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 1LE 1 48 1OE TSTG Storage Temperature 65 to +150 C 1Q1 2 47 1D1 IOUT DC Output Current 50 to +50 mA 1Q2 3 46 1D2 IIK Continuous Clamp Current, 50 mA VI < 0 or VI > VCC 4 GND 45 GND IOK Continuous Clamp Current, VO < 0 50 mA 1Q3 44 1D3 5 ICC Continuous Current through each 100 mA ISS VCC or GND 1Q4 6 1D4 43 NOTES: VCC 7 42 VCC 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation 1D5 1Q5 8 41 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating 1Q6 1D6 9 40 conditions for extended periods may affect reliability. 2. VCC terminals. GND 10 39 GND 3. All terminals except VCC. 1Q7 11 1D7 38 12 1D8 1Q8 37 CAPACITANCE (TA = +25C, F = 1.0MHz) (1) 2Q1 2D1 13 36 Symbol Parameter Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 5 7 pF 2Q2 35 2D2 14 COUT Output Capacitance VOUT = 0V 7 9 pF GND 15 34 GND CI/O I/O Port Capacitance VIN = 0V 7 9 pF 2Q3 16 33 2D3 NOTE: 1. As applicable to the device type. 2D4 2Q4 17 32 31 VCC VCC 18 PIN DESCRIPTION 2Q5 2D5 19 30 Pin Names Description 29 2D6 (1) 2Q6 20 x D x Data Inputs xLE Latch Enable Inputs 28 GND GND 21 x Q x 3-State Outputs 22 2D7 2Q7 27 xOE 3-State Output Enable Input (Active LOW) 2Q8 23 26 2D8 NOTE: 2LE 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. 2OE 24 25 (1) FUNCTION TABLE (EACH 8-BIT SECTION) SSOP/ TSSOP TOP VIEW Inputs Outputs xOE xLE xDx xQx LH H H LH L L HX X Z (2) LL X Q o NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High Impedance 2. Output level before the indicated steady-state input conditions were established. 2