IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 16-BIT EDGE- IDT74ALVCH162374 TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology This 16-bit edge-triggered D-type flip-flop is built using advanced dual metal Typical tSK(o) (Output Skew) < 250ps CMOS technology. The ALVCH162374 is particularly suitable for implementing ESD > 2000V per MIL-STD-883, Method 3015 > 200V using buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can machine model (C = 200pF, R = 0) be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of VCC = 3.3V 0.3V, Normal Range the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up VCC = 2.7V to 3.6V, Extended Range at the data (D) inputs. OE can be used to place the eight outputs in either a normal VCC = 2.5V 0.2V logic state (high or low logic levels) or a high-impedance state. In the high- CMOS power levels (0.4 W typ. static) impedance state, the outputs neither load nor drive the bus lines significantly. Rail-to-Rail output swing for increased noise margin The high-impedance state and the increased drive provide the capability to Available in TSSOP package drive bus lines without need for interface or pullup components. OE does not affect internal operations of the flip-flop. Old data can be retained or new data DRIVE FEATURES: can be entered while the outputs are in the high-impedance state. Balanced Output Drivers: 12mA The ALVCH162374 has series resistors in the device output structure which Low switching noise will significantly reduce line noise when used with light loads. This driver has been designed to drive 12mA at the designated threshold levels. The ALVCH162374 has bus-hold which retains the inputs last state APPLICATIONS: whenever the input goes to a high impedance. This prevents floating inputs and 3.3V high speed systems eliminates the need for pull-up/down resistor. 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM 1 24 2OE 1OE 48 25 2CLK 1CLK C1 C1 2 13 1Q1 2Q1 47 36 1D1 1D 1D 2D1 TO 7 OTHER CHANNELS TO 7 OTHER CHAN- NELS IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JULY 2009 1 2009 Integrated Device Technology, Inc. DSC-4565/5IDT74ALVCH162374 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP INDUSTRIAL TEMPERATURE RANGE (1) PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS Symbol Description Max Unit (2) VTERM Terminal Voltage with Respect to GND 0.5 to +4.6 V (3) VTERM Terminal Voltage with Respect to GND 0.5 to VCC+0.5 V 1CLK 1OE 1 48 TSTG Storage Temperature 65 to +150 C 1Q1 47 2 1D1 IOUT DC Output Current 50 to +50 mA 1Q2 3 46 1D2 IIK Continuous Clamp Current, 50 mA VI < 0 or VI > VCC 4 45 GND GND IOK Continuous Clamp Current, VO < 0 50 mA 1D3 1Q3 5 44 ICC Continuous Current through each 100 mA ISS VCC or GND 1D4 1Q4 6 43 NOTES: VCC 7 42 VCC 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation 1D5 1Q5 8 41 of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating 1Q6 9 1D6 40 conditions for extended periods may affect reliability. 2. VCC terminals. GND GND 10 39 3. All terminals except VCC. 1Q7 1D7 11 38 CAPACITANCE (TA = +25C, F = 1.0MHz) 1Q8 12 37 1D8 (1) Symbol Parameter Conditions Typ. Max. Unit 2D1 2Q1 13 36 CIN Input Capacitance VIN = 0V 5 7 pF 2Q2 35 2D2 14 COUT Output Capacitance VOUT = 0V 7 9 pF 15 34 GND GND CI/O I/O Port Capacitance VIN = 0V 7 9 pF NOTE: 2Q3 16 33 2D3 1. As applicable to the device type. 2D4 2Q4 17 32 31 VCC VCC 18 PIN DESCRIPTION 2D5 2Q5 19 30 Pin Names Description (1) x D x Data Inputs 29 2D6 2Q6 20 xCLK Clock Inputs 28 GND GND 21 x Q x 3-State Outputs 2D7 2Q7 22 27 xOE 3-State Output Enable Input (Active LOW) 23 26 2D8 2Q8 NOTE: 1. These pins haveBus-Hol. All other pins are standard inputs, outputs, or I/Os. 2CLK 24 2OE 25 (1) FUNCTION TABLE (EACH FLIP-FLOP) TSSOP TOP VIEW Inputs Outputs xOE xCLK xDx xQx L HH L LL (2) L H or L X Q o HX X Z NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High Impedance = LOW-to-HIGH transition 2. Output level before the indicated steady-state input conditions were established. 2