74ALVCH16841DGG,11 NXP

INTEGRATED CIRCUITS 74ALVCH16841 20-bit bus interface D-type latch (3-State) Product specification 1998 Jul 27 IC24 Data Handbook Philips Semiconductors Product specification 20-bit bus interface D-type latch (3-State) 74ALVCH16841 FEATURES PIN CONFIGURATION Wide supply voltage range of 1.2V to 3.6V 1OE 1 56 1LE Complies with JEDEC standard no. 8-1A 1Q0 2 55 1D0 Wide supply voltage range of 1.2V to 3.6V 1Q1 3 54 1D1 GND 4 53 GND CMOS low power consumption 1Q2 5 52 1D2 Direct interface with TTL levels 1Q3 6 51 1D3 TM MULTIBYTE flow-through standard pin-out architecture 7 50 V V CC CC Low inductance multiple V and GND pins for minimum noise 8 49 1D4 1Q4 CC and ground bounce 1Q5 9 48 1D5 1Q6 10 Current drive 24 mA at 3.0 V 47 1D6 GND 11 46 GND All inputs have bus hold circuitry 1Q7 12 45 1D7 Output drive capability 50 transmission lines 85C 1Q8 13 44 1D8 3-State non-inverting outputs for bus oriented applications 1Q9 14 43 1D9 2Q0 15 42 2D0 DESCRIPTION 2Q1 16 41 2D1 The 74ALVCH16841 has two 10-bit D-type latch featuring separate 2Q2 17 40 2D2 D-type inputs for each latch and 3-State outputs for bus oriented GND 18 39 GND applications. The two sections of each register are controlled independently by the latch enable (nLE) and output enable (nOE) 2Q3 19 38 2D3 control gates. 2Q4 20 37 2D4 When nOE is LOW, the data in the registers appears at the outputs. 2Q5 21 36 2D5 When nOE is High the outputs are in High-impedance OFF state. V 22 35 V CC CC Operation of the nOE input does not affect the state of the flip-flops. 2Q6 23 34 2D6 The 74ALVCH16841 has active bus hold circuitry which is provided 2Q7 24 33 2D7 to hold unused or floating data inputs at a valid logic level. This 32 GND GND 25 feature eliminates the need for external pull-up or pull-down 2Q8 26 31 2D8 resistors. 2Q9 27 30 2D9 2OE 28 29 2LE SA00076 QUICK REFERENCE DATA GND = 0V T = 25C t = t 2.5ns amb r f SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay V = 2.5V, C = 30pF 2.5 CC L t /t ns PHL PLH nD to nQ V = 3.3V, C = 50pF 2.4 n n CC L Propagation delay V = 2.5V, C = 30pF 2.5 CC L t /t ns PHL PLH nLE to nQ V = 3.3V, C = 50pF 2.4 n CC L C Input capacitance 5.0 pF I Outputs enabled 19 11 CC PowerPower dissidissipationation cacapacitanceacitance perer bufbufferfer VV = = GNDGND toto VV pFF PDPD II CCCC Outputs disabled 3 NOTES: 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P = C V f + (C V f ) where: f = input frequency in MHz C = output load capacitance in pF D PD CC i L CC o i L 2 f = output frequency in MHz V = supply voltage in V (C V f ) = sum of outputs. o CC L CC o ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER 56-Pin Plastic TSSOP Type II 40C to +85C 74ALVCH16841 DGG ACH16841 DGG SOT364-1 2 1998 Jul 27 853-2093 19785