74ALVCH16374DGG;11 Nexperia

74ALVCH16374 2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop 3-state Rev. 7 23 November 2021 Product data sheet 1. General description The 74ALVCH16374 is a 16-bit edge-triggered D-type flip-flop with bus hold inputs and 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. This device is fully specified for partial power down applications using I . The I OFF OFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.. 2. Features and benefits Wide supply voltage range from 1.2 V to 3.6 V Complies with JEDEC standards: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8C (2.7 V to 3.6 V) CMOS low power dissipation MULTIBYTE flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels All data inputs have bus hold Latch-up performance exceeds 100 mA per JESD 78 Class II Level B Output drive capability 50 transmission lines at 85 C I circuitry provides partial Power-down mode operation OFF Current drive 24 mA at V = 3.0 V CC ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V Specified from -40 C to +85 C 3. Ordering information Table 1. Ordering information Type number Temperature range Package Name Description Version 74ALVCH16374DGG -40 C to +85 C TSSOP48 plastic thin shrink small outline package SOT362-1 48 leads body width 6.1 mmNexperia 74ALVCH16374 2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop 3-state 4. Functional diagram 1 1 24 1OE 1EN 48 1CP C1 1OE 2OE 24 2OE 2EN 47 1D0 1Q0 2 25 2CP C2 46 1D1 1Q1 3 47 2 44 1D2 1Q2 5 1D0 1D 1 1Q0 46 3 43 1D3 1Q3 6 1D1 1Q1 44 5 41 1D4 1Q4 8 1D2 1Q2 43 6 40 1D5 1Q5 9 1D3 1Q3 41 8 38 1D6 1Q6 11 1D4 1Q4 40 9 37 1D7 1Q7 12 1D5 1Q5 38 11 36 2D0 2Q0 13 1D6 1Q6 37 12 35 2D1 2Q1 14 1D7 1Q7 36 13 33 2D2 2Q2 16 2D0 2D 2 2Q0 35 14 32 2D3 2Q3 17 2D1 2Q1 33 16 30 2D4 2Q4 19 2D2 2Q2 32 17 29 2D5 2Q5 20 2D3 2Q3 30 19 27 2D6 2Q6 22 2D4 2Q4 29 20 26 2D7 2Q7 23 2D5 2Q5 27 22 2D6 2Q6 1CP 2CP 26 23 2D7 2Q7 48 25 001aal770 001aal772 Fig. 1. Logic symbol Fig. 2. IEC logic symbol V CC data input to internal circuit mna705 Fig. 3. Bus hold circuit 1D0 D Q 1Q0 2D0 D Q 2Q0 CP CP FF1 FF9 1CP 2CP 1OE 2OE to 7 other channels to 7 other channels 001aal771 Fig. 4. Logic diagram 74ALVCH16374 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2021. All rights reserved Product data sheet Rev. 7 23 November 2021 2 / 13