74ALVCH16601 18-bit universal bus transceiver 3-state Rev. 3 13 August 2018 Product data sheet 1. General description The 74ALVCH16601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. To ensure the high impedance state during power up or power down, OEBA and OEAB should be tied to V through a pullup resistor the minimum value of the resistor is determined by the CC current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. 2. Features and benefits CMOS low power consumption MultiByte flow-through standard pin-out architecture Low inductance multiple V and GND pins for minimum noise and ground bounce CC Direct interface with TTL levels Bus hold on data inputs Output drive capability 50 transmission lines at 85 C Current drive 24 mA at 3.0 V Complies with JEDEC standards: JESD8-5 (2.3 V to 2.7 V) JESD8B/JESD36 (2.7 V to 3.6 V) ESD protection: HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V CDM JESD22-C101E exceeds 1000 V 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74ALVCH16601DGG 40 C to +85 C TSSOP56 plastic thin shrink small outline package SOT364-1 56 leads body width 6.1 mmNexperia 74ALVCH16601 18-bit universal bus transceiver 3-state 4. Functional diagram 1 OEAB EN1 56 CEAB G2 55 CPAB 2C3 2 LEAB C3 G2 27 OEBA EN4 29 CEBA G5 A0 B0 3 54 30 CPBA 5C6 A1 B1 28 5 52 LEBA C6 A2 B2 6 51 G5 A3 B3 8 49 3 54 A4 B4 A0 B0 3D 1 1 9 48 A5 B5 4 1 6D 10 47 5 52 A6 B6 A1 B1 12 45 6 51 A7 B7 A2 B2 13 44 8 49 A8 B8 A3 B3 14 43 9 48 A9 B9 A4 B4 15 42 10 47 A10 B10 A5 B5 16 41 12 45 A11 B11 A6 B6 17 40 13 44 A12 B12 A7 B7 19 38 14 43 A13 B13 A8 B8 20 37 15 42 A14 B14 A9 B9 21 36 16 41 A15 B15 A10 B10 23 34 17 40 A16 B16 A11 B11 24 33 19 38 A17 B17 A12 B12 26 31 20 37 A13 B13 21 36 OEAB OEBA A14 B14 1 27 23 34 LEAB LEBA A15 B15 2 28 24 33 CPAB CPBA A16 B16 55 30 26 31 CEAB CEBA A17 B17 55 29 aaa-028853 aaa-028854 Fig. 1. Logic symbol Fig. 2. IEC logic symbol V CC data input to internal circuit 001aal733 Fig. 3. Bus hold circuit 74ALVCH16601 All information provided in this document is subject to legal disclaimers. Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 3 13 August 2018 2 / 15