74ALVCH16500DGG,11 NXP

INTEGRATED CIRCUITS 74ALVCH16500 18-bit universal bus transceiver (3-State) Product specification 1998 Sep 24 Supersedes data of 1998 Aug 31 IC24 Data Handbook Philips Semiconductors Product specification 18-bit universal bus transceiver (3-State) 74ALVCH16500 FEATURES DESCRIPTION The 74ALVCH16500 is a high-performance CMOS product. Complies with JEDEC standard no. 8-1A This device is an 18-bit universal transceiver featuring non-inverting CMOS low power consumption 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE and AB Direct interface with TTL levels OE ), latch enable (LE and LE ), and clock (CP and CP ) BA AB BA AB BA inputs. For A-to-B data flow, the device operates in the transparent Current drive 24 mA at 3.0 V mode when LE is High. When LE is Low, the A data is latched if AB AB All inputs have bushold circuitry CP is held at a High or Low logic level. If LE is Low, the A-bus AB AB data is stored in the latch/flip-flop on the High-to-Low transition of Output drive capability 50 transmission lines 85C CP . When OE is High, the outputs are active. When OE is AB AB AB TM MULTIBYTE flow-through standard pin-out architecture Low, the outputs are in the high-impedance state. Low inductance multiple V and ground pins for minimum noise Data flow for B-to-A is similar to that of A-to-B but uses OE , LE CC BA BA and ground bounce and CP . The output enables are complimentary (OE is active BA AB High, and OE is active Low). BA To ensure the high impedance state during power up or power down, OE should be tied to V through a pullup resistor and BA CC OE should be tied to GND through a pulldown resistor the AB minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. QUICK REFERENCE DATA GND = 0V T = 25C t = t = 2.5ns amb r f SYMBOL PARAMETER CONDITIONS TYPICAL UNIT Propagation delay t /t V = 2.5V, C = 30pF 3.1 ns CC L PHL PLH An, Bn to Bn, An V = 3.3V, C = 50pF 2.9 CC L C Input/output capacitance 8.0 pF I/O C Input capacitance 4.0 pF I Outputs enabled 21 11 CC PowerPower dissidissipationation cacapacitanceacitance perer latchlatch VV = = GNDGND toto VV pFF PDPD II CCCC Outputs disabled 3 NOTES: 1. C is used to determine the dynamic power dissipation (P in W): PD D 2 2 P = C V f + (C V f ) where: f = input frequency in MHz C = output load capacitance in pF D PD CC i L CC o i L 2 f = output frequency in MHz V = supply voltage in V (C V f ) = sum of outputs. o CC L CC o ORDERING INFORMATION PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA DWG NUMBER 56-Pin Plastic TSSOP Type II 40C to +85C 74ALVCH16500 DGG SOT364-1 2 1998 Sep 24 8533-2125 20079